AMD SC1200 Source EOP width, Host upstream, Receiver data jitter tolerance for paired, VSE Min

32579BElectrical Specifications

Table 9-31. USB Timing Parameters (Continued)

Symbol	Parameter	Min	Max	Unit	Figure	Comments
tUSB_DJU22	Source differential driver jitter for paired	–150	150	ns	9-39	Function (downstream),
	transactions					Note 4
tUSB_SE2	Source EOP width	1.25	1.5	μs	9-40	Note 4, Note 5
tUSB_DE2	Differential to EOP transition skew	–40	100	ns	9-40	Note 5
tUSB_RJD21	Receiver data jitter tolerance for con-	–152	152	ns	9-41	Host (upstream),
	secutive transactions					Note 4
tUSB_RJD22	Receiver data jitter tolerance for paired	–200	200	ns	9-41	Host (upstream),
	transactions					Note 4
tUSB_RJU21	Receiver data jitter tolerance for con-	–75	75	ns	9-41	Function (downstream),
	secutive transactions					Note 4
tUSB_RJU22	Receiver data jitter tolerance for paired	–45	45	ns	9-41	Function (downstream),
	transactions					Note 4
Low Speed Receiver EOP Width (Note 5)
tUSB_RE21	Must reject as EOP		330	ns	9-39
tUSB_RE22	Must accept as EOP	675		ns	9-39

Note 1. Unless otherwise specified, all timings use a 50 pF capacitive load (CL) to ground. Note 2. Full-speed timing has a 1.5 KΩ pull-up to 2.8 V on the DPOS_Port1,2,3 lines.

Note 3. Timing difference between the differential data signals (DPOS_PORT1,2,3 and DNEG_PORT1,2,3). Note 4. Measured at the crossover point of differential data signals (DPOS_PORT1,2,3 and DNEG_PORT1,2,3).

Note 5. EOP is the End of Packet where DPOS_PORTt = DNEG_PORT = SE0. SE0 occurs when output level voltage ≤

VSE (Min).

Note 6. CL = 350 pF.

418 AMD Geode™ SC1200/SC1201 Processor Data Book