AMD SC1200, SC1201 manual Direct Mode and Capture Mode Configurations

32579B Video Processor Module

7.2.1.1Direct Video Mode

As stated previously, Direct Video mode is on by default so no registers need to be programmed to support this mode other than to select the direct video data at the video mux. The video mux control register is located at F4BAR0+Mem- ory Offset 400h[1:0].

GenLock

Because video input data from the VIP is sent directly, with- out significant buffering, field-to-field synchronization is required with the TV encoder, and frame-to-field synchroni- zation is required with the GX1 module’s graphics data. This synchronization is known as GenLock. The GenLock registers are located at F4BAR0+Memory Offset 420h and 424h.

The odd/even fields of the video input data must be syn- chronized with the odd/even fields produced by the TV encoder. This field-to-field synchronization is accomplished by setting the SG_GENLOCK_EN bit (F4BAR0+Memory Offset 420h[0]). Field-to-field synchronization is only required once.

The GenLock control hardware is used to synchronize the video input’s field with the GX1 module’s graphics frame. The graphics data is always sent full frame. For the Gen- Lock function to perform correctly, the GX1 module’s Dis- play Controller must be programmed to have a slightly faster frame time then the video input’s field time. This is best accomplished by programming the GX1 module’s Dis- play Controller with a few less (three to five) horizontal lines then the VIP interface. GenLock is accomplished by stop- ping the clock driving the GX1 module’s graphics frame

until the VIP vertical sync occurs (plus some additional delay, via F4BAR0+Memory Offset 424h).

The GenLock function provides a timeout feature (GENLOCK_TOUT_EN, F4BAR0+Memory Offset 420h[4]) in case the video port input clock stops due to a problem with incoming video.

7.2.1.2Direct VBI Mode

Direct VBI mode operation is very similar to Direct Video mode and is also on by default. The VBI mux control is located at F4BAR0+Memory Offset 400h[2]. Specific VBI lines may be blocked or nulled before they are sent to the TV Encoder, (F4BAR2+Memory Offsets 18h and 1Ch). VBI GenLock is also required for Direct VBI mode to perform correctly. See Section 7.2.1.1 for a more detailed explana- tion on GenLock.

7.2.1.3Capture Video Mode

Capture Video mode is a process for bus mastering Video data received from the VIP block to the GX1 module’s Video Frame Buffer. The GX1 module’s Display Controller then moves the data from the Video Frame Buffer to the Video Formatter. Usually Capture Video mode is used because the data coming in from the VIP block is interlaced and has a 30 Hz refresh rate (NTSC format) and the output device, CRT monitor or TFT panel, is progressive and has a 60 to 85 Hz refresh rate. The Capture Video mode pro- cess must convert the interlaced data to progressive data and change the frames per second. There are two methods to perform the interlaced to progressive conversion; Bob and Weave. Each method uses a different mechanism to up the refresh rate.

Table 7-1. Direct Mode and Capture Mode Configurations

Video	VBI	Output
Mode	Mode	Interface	Comments
Direct	Direct	TV	Video data must be full frame. GX1 graphics/video frame buffers are not used.
Direct	Capture	TV	Video data must be full frame. VBI data can be decoded, turned into graphic
			information and placed in the GX1 module’s graphics frame buffer for display,
			or it can be manipulated and placed into the video frame buffer as modified VBI
			data.
Capture	Direct	TV	Unsupported
Capture	Capture	TV, CRT,	The only mode available for CRT and TFT displays and only necessary for TV
		TFT	displays when video data is less then full frame. CRT and TFT displays do not
			allow for VBI at all. However, VBI data can be decoded, turned into graphic
			information and placed in the GX1 module’s graphics frame buffer for display.
			Restriction: The GX1 module’s video frame buffer cannot be used to send both
			video and VBI data.

316 AMD Geode™ SC1200/SC1201 Processor Data Book