AMD SC1200 Frame# Trdy#, Irdy#, ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP#, DMA Controller

32579BCore Logic Module

PCI	TCS	Sub-ISA	TCP	PCI
	pull-up

FRAME#

TRDY#, IRDY#

GNT[x]

ROMCS#, DOCCS#,

IOCS0#, IOCS1#

PAR,

DEVSEL#,STOP#

AD[31:0],

C/BE[3:0]#

Figure 6-6. PCI Change to Sub-ISA and Back

6.2.6AT Compatibility Logic

The Core Logic module integrates:

•Two 8237-equivalent DMA controllers with full 32-bit addressing

•Two 8259A-equivalent interrupt controllers providing 13 individually programmable external interrupts

•An 8254-equivalent timer for refresh, timer, and speaker logic

•NMI control and generation for PCI system errors and all parity errors

•Support for standard AT keyboard controllers

•Positive decode for the AT I/O register space

•Reset control

6.2.6.1DMA Controller

The Core Logic module supports industry standard DMA architecture using two 8237-compatible DMA controllers in cascaded configuration. The DMA functions supported by the Core Logic module include:

•Standard seven-channel DMA support (Channels 5 through 7 are not supported)

•32-bit address range support via high page registers

•IOCHRDY extended cycles for compatible timing trans- fers

•Internal Sub-ISA bus master device support using cascade mode

•NMI control and generation for PCI system errors and all parity errors.

Note: DMA interface signals are not available externally.

DMA Channels

The Core Logic module supports seven DMA channels using two standard 8237-equivalent controllers. DMA Con- troller 1 contains Channels 0 through 3 and supports 8-bit I/O adapters. These channels are used to transfer data between 8-bit peripherals and PCI memory or 8/16-bit ISA memory. Using the high and low page address registers, a full 32-bit PCI address is output for each channel so they can all transfer data throughout the entire 4 GB system address space. Each channel can transfer data in 64 KB pages. Software initiated DMA requests are not supported.

DMA Controller 2 contains Channels 4 through 7. Channel 4 is used to cascade DMA Controller 1, so it is not available externally. Channels 5 through 7 support 16-bit I/O adapt- ers to transfer data between 16-bit I/O adapters and 16-bit system memory. Using the high and low page address reg- isters, a full 32-bit PCI address is output for each channel so they can all transfer data throughout the entire 4 GB system address space. Each channel can transfer data in 128 KB pages. Channels 5, 6, and 7 transfer 16-bit WORDs on even byte boundaries only. Channels 5 through 7 are not supported.

152 AMD Geode™ SC1200/SC1201 Processor Data Book