AMD SC1200 Relevant Serial Ports 1 and 2 Registers, Serial Ports 1 and 2 Configuration Register

32579B SuperI/O Module

5.4.2.4LDN 03h and 08h - Serial Ports 1 and 2

Serial Ports 1 and 2 are identical, except for their reset val- ues.

Serial Port 1 is designated as LDN 03h and Serial Port 2 as LDN 08h. Table 5-11lists the configuration registers which

affect Serial Ports 1 and 2. Only the last register (F0h) is described here (Table 5-12). See Table 5-3 "Standard Con- figuration Registers" on page 95 for descriptions of the oth- ers.

Table 5-11. Relevant Serial Ports 1 and 2 Registers

			Reset Value
Index	Type	Configuration Register or Action	Port 1	Port 2
30h	R/W	Activate. See also bit 0 of the SIOCF1 register.	00h	00h
60h	R/W	Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b.	03h	02h
61h	R/W	Base Address LSB register. Bit [2:0] (for A[2:0]) are RO, 000b.	F8h	F8h
70h	R/W	Interrupt Number.	04h	03h
71h	R/W	Interrupt Type. Bit 1 is R/W; other bits are RO.	03h	03h
74h	RO	Report no DMA assignment.	04h	04h
75h	RO	Report no DMA assignment.	04h	04h
F0h	R/W	Serial Ports 1 and 2 Configuration register.	02h	02h

Table 5-12. Serial Ports 1 and 2 Configuration Register

Bit	Description
Index F0h	Serial Ports 1 and 2 Configuration Register (R/W)	Reset Value: 02h

7Bank Select Enable. Enables bank switching for Serial Ports 1 and 2.

0:Disabled. (Default)

1:Enabled.

6:3 Reserved.

2Busy Indicator. (RO) This bit can be used by power management software to decide when to power-down Serial Ports 1 and 2 logical devices.

0:No transfer in progress. (Default)

1:Transfer in progress.

1Power Mode Control. When the logical device is active in:

0:Low power mode - Serial Ports 1 and 2 Clock disabled. The output signals are set to their default states. Registers are maintained. (Unlike Active bit in Index 30h that also prevents access to Serial Ports 1 or 2 registers.)

1:Normal power mode - Serial Ports 1 and 2 clock enabled. Serial Ports 1 and 2 are functional when the respective logical devices are active. (Default)

0TRI-STATE Control. This bit controls the TRI-STATE status of the device output pins when it is inactive (disabled).

0:Disabled. (Default)

1:Enabled when device inactive.

102 AMD Geode™ SC1200/SC1201 Processor Data Book