AMD SC1200, SC1201 Memory Controller Timing Parameters, SDCLK30, Sdclkout high time, 13.5, 378

32579BElectrical Specifications

Table 9-12. Memory Controller Timing Parameters

Symbol	Parameter	Min	Max	Unit	Comments
t1	Control output valid from SDCLK[3:0]	-3.0 + (x * y)	0.1 + (x * y)	ns	Note 1, Note 2
t2	MA[12:0], BA[1.0] output valid from	-3.2 + (x * y)	0.1 + (x * y)	ns	Note 2
	SDCLK[3:0]
t3	MD[63:0] output valid from SDCLK[3:0]	-2.2 + (x * y)	0.7 + (x * y)	ns	Note 2
t4	MD[63:0] read data in setup to SDCLK_IN	1.3		ns
t5	MD[63:0] read data hold to SDCLK_IN	2.0		ns
t6	SDCLK[3:0], SDCLK_OUT cycle time	8.3	13.5	ns
t7	SDCLK[3:0], SDCLK_OUT fall/rise time		2	ns
	between (VOLD-VOHD)
t9	SDCLK_IN fall/rise time between		2	ns
	(VILD-VIHD)
t10	SDCLK[3:0], SDCLK_OUT high time	3.0
t11	SDCLK[3:0], SDCLK_OUT low time	2.5)

Note 1. Control output includes all the following signals: RASA#, CASA#, WEA#, CKEA, DQM[7:0], and CS[1:0]#.

Load = 50 pF, VCORE = 1.8V, VIO = 3.3V, @25oC.

Note 2. Use the Min/Max equations [value+(x * y)] to calculate the actual output value.

x is the shift value which is applied to the SHFTSDCLK field, and y is 0.45 the core clock period.

Note that the SHFTSDCLK field = GX_BASE+Memory Offset 8404h[5:3]. Refer to the AMD Geode™ GX1 Proces- sor Data Book for more information.

For example, for a 266 MHz SC1200/SC1201 processor running an 88.7 MHz SDRAM clock, with a shift value of 3: t1 Min = -3 + (3 * (3.76 * 0.45)) = 2.08 ns

t1 Max = 0.1 + (3 * (3.76 * 0.45)) = 5.18 ns

378 AMD Geode™ SC1200/SC1201 Processor Data Book