Publication ID 32579B
AMD Geode SC1200/SC1201 Processor Data Book
Advanced Micro Devices, Inc. All rights reserved
Contacts Trademarks
Contents
Electrical Specifications
Package Specifications
Core Logic Module
Video Processor Module
Power Supply Connections
Typical Battery Configuration
Typical Battery Current Normal Operation Mode
ACCESS.bus Data Transaction
Multiword DMA Data Transfer Timing Diagram 405
USB Data Signal Rise and Fall Timing Diagram 419
USB EOP Width Timing Diagram 420
Fast IR Timing MIR and FIR Diagram 422
424
425
426
427
32579B
IRCP/SP3 Configuration Register
Serial Ports 1 and 2 Configuration Register
ACB1 and ACB2 Configuration Register
Parallel Port Configuration Register
Banks 0 and 1 Common Control and Status Registers 118
119
166
167
Pciusb USB PCI Configuration Register Summary
F0BAR0+I/O Offset Gpio Configuration Registers
F2BAR4+I/O Offset IDE Controller Configuration Registers
F3 PCI Header Registers for Audio Configuration
384
400
402
404
General Description
Video Processor
Core Logic
SuperI/O
Features
General Features
GX1 Processor Module
Video Processor Module
Other Features
Core Logic Module
Nand Eeprom
SuperI/O Module
32579B
GX1 Module
Memory Controller
Architecture Overview 32579B
Width Memory Offset Bits Type Name/Function Reset Value
SC1200/SC1201 Processor Memory Controller Register Summary
SC1200/SC1201 Processor Memory Controller Registers
MCMEMCNTRL2 R/W
Bit Description GXBASE+8408h-840Bh
Mcbankcfg R/W
Rsvd Reserved. Write as 0070h
Rsvd Reserved. Write as GXBASE+840Ch-840Fh
Mcgbaseadd R/W
Mcdradd R/W
Mcdracc R/W
Fast-PCI Bus
Display
1 GX1 Module Interface
Video Input Port
Clock, Timers, and Reset Logic
Reset Logic
Power-On Reset
System Reset
32579B
Signal Definitions 32579B
AMD Geode
SC1200/SC1201
Processor
USB
Jtag Interface
Signal Definitions Legend
Mnemonic Definition
SC1200/SC1201
Configuration
BGU481 Ball Assignment Sorted by Ball Number
REQ0#
GNT0#
GPIO7
AFD#/DSTRB#
PAR
GPIO12
FTRDY#
AC1 IDEDATA1
Buffer1 Power Signal Name
Ball Buffer Power Signal Name
BGU481 Ball Assignment Sorted Alphabetically by Signal Name
Signal Name Ball No
F30
FC/BE0# D21
C11
FC/BE1# B17
MD23
MD24
MD25 AC28
MD26 AC29
C24
N13, N14, N18
A2, A30, B2, B13
F31
Nominal External PU/PD Strap Settings
Strap Options
Strap Options
Multiplexing Configuration
Two-Signal/Group Multiplexing
Default Alternate Ball No Signal Configuration
TFT, CRT, PCI, GPIO, System
ACCESS.bus
Internal Test
AC97 Fpci Monitoring
Three-Signal/Group Multiplexing
Four-Signal/Group Multiplexing
Gpio UART2 IDE2
Signal Descriptions
Signal Name Ball No Type Description Mux
Maximum Core Clock Multiplier. These strap signals
Boot ROM is 16 Bits Wide. This strap signal enables
Memory Interface Signals
Column Address Strobe. RAS#, CAS#, WE# and CKE
Video Port Interface Signals
4 CRT/TFT Interface Signals
Digital RGB Data to TFT
TV Interface Signals
Super Video Chrominance. S-Video chrominance sig
Current Compensation for TV DAC. a 0.1 µF to 1.2 µF
ACCESS.bus Interface Signals
PCI Bus Interface Signals
INTA#
INTB#
INTC#
INTD# AA2
STOP#
LOCK#
DEVSEL#
BHE#
PERR#
SERR#
REQ1#
REQ0#
Sub-ISA Interface Signals
Low Pin Count LPC Bus Interface Signals
IDE Interface Signals
Universal Serial Bus USB Interface Signals
Serial Ports UARTs Interface Signals
Parallel Port Interface Signals
Fast Infrared IR Port Interface Signals
15 AC97 Audio Interface Signals
Power Management Interface Signals
General Purpose Wakeup I/Os. These signals each
Serial Bus Synchronization. This bit is asserted to syn
Suspend Power Plane Control 1 and 2. Control signal
PWRBTN# AH5
PWRCNT1 AK6
PWRCNT2 AL7
Gpio Interface Signals
Debug Monitoring Interface Signals
Jtag Interface Signals
Fast-PCI Bus Monitoring Signals. When enabled, this
System Management Interrupt. This is the input to
Test and Measurement Interface Signals
PLL6, PLL5 and PLL2 Bypass. These signals are used
Memory Internal Test Signals. These signals are used
Thermal Diode Positive / Negative. These signals are for
Power and Ground Connections1
Configuration Block Addresses
General Configuration Block Register Summary
General Configuration Block 32579B
Width Offset Bits
Ball # Internal Test Signals Name Add’l Dependencies
Other Signal Add’l Dependencies
PMR27
Fpcimon
General Configuration Block
Ball # IDE Signals CRT, Gpio and TFT Signals Name
PP/ACB1/FPCI TFT/VOP
Name Add’l Dependencies
Ball # Gpio Signals LPC Signals Name Add’l Dependencies
32579BGeneral Configuration Block
Reserved
General Configuration Block
Offset 3Eh-3Fh Configuration Base Address Register CBA RO
Offset 38h Interrupt Selection Register Intsel R/W
Offset 3Dh Revision Register REV RO
Watchdog Timer
Functional Description
Watchdog Registers
Watchdog Interrupt
3describes the Watchdog registers
Usage Hints
High-Resolution Timer
High-Resolution Timer Registers
Watchdog Status Register Wdsts R/WC Reset Value 00h
Offset 05h-07h
Reset Value xxxxxxxxh
Tmclksel Timer Clock Select
Tmen Timer Interrupt Enable
Bit Description Offset 08h-0Bh
Clock Generators and PLLs
1 27 MHz Crystal Oscillator
Crystal Oscillator Circuit Components
Component Parameters Values Tolerance
2 GX1 Module Core Clock
Internal Fast-PCI Clock
Core Clock Frequency
Strapped Core Clock Frequency
SuperI/O Clocks
Core Logic Module Clocks
Video Processor Clocks
Clock Generator Configuration
Clock Registers
Clock generator and PLL registers are described in Table
1514
Reserved. Must be set to 1110
33.3 MHz
66.7 MHz
Outstanding Features
ISA
AB1C AB1D AB2C AB2D
PC98 and Acpi Compliant
Parallel Port
Serial Port
Serial Port 3 / Infrared IR Communication Port
Access
Signals
Internal Internal Signals
Module Architecture
Configuration Structure / Access
SIO Configuration Options
Index-Data Register Pair
LDN Assignments
Default Configuration Setup
Address Decoding
Standard Configuration Registers
SIO Control and Configuration Registers
Logical Device Control and Configuration Registers
Standard Logical Device Configuration Registers
Standard Configuration Registers
Index F0h-FEh Logical Device Configuration R/W
32579BSuperI/O Module
DMA Channel Select 1 R/W
SIO Control and Configuration Registers
SIO Control and Configuration Register Map
Index Type Name Power Rail Reset Value
SID. SIO ID
Logical Device Control and Configuration
Relevant RTC Configuration Registers
RTC Configuration Registers
Relevant SWC Registers
LDN 01h System Wakeup Control
Base Address MSB register
10. IRCP/SP3 Configuration Register
Relevant IRCP/SP3 Registers
12. Serial Ports 1 and 2 Configuration Register
Serial Ports 1 and 2 Configuration register
11. Relevant Serial Ports 1 and 2 Registers
LDN 03h and 08h Serial Ports 1
14. ACB1 and ACB2 Configuration Register
LDN 05h and 06h ACCESS.bus Ports 1
ACB1 and ACB2 Configuration register
13. Relevant ACB1 and ACB2 Registers
16. Parallel Port Configuration Register
15. Relevant Parallel Port Registers
X32I External X32O Battery = 0.1 μF
Real-Time Clock RTC
Bus Interface RTC Clock Generation
17. Crystal Oscillator Circuit Components
Signal Parameters
External Elements
Oscillator Startup
External Oscillator
Alarms
Timekeeping Data Format
Daylight Saving
Leap Years
Power Supply
18. System Power States
Battery-Backed RAMs and Registers
Interrupt Handling
110
RTC Registers
19. RTC Register Map
20. RTC Registers
Index Type Name
Index 05h Hours Alarm Register Hora R/W
Index 04h Hours Register HOR R/W
CRD is
112
Index Programmable Month Alarm Register Mona R/W
Index 0Ch RTC Control Register C CRC RO
Index Programmable Century Register CEN R/W
AMD Geode SC1200/SC1201 Processor Data Book 113
21. Divider Chain Control / Test Selection
22. Periodic Interrupt Rate Encoding
23. BCD and Binary Formats
Parameter BCD Format Binary Format
0Eh 7Fh Battery-backed general-purpose Byte RAM
00h 7Fh Battery-backed general-purpose Byte RAM
RTC General-Purpose RAM Map 24. Standard RAM Map
25. Extended RAM Map
System Wakeup Control SWC
Event Detection
26. Time Range Limits for Ceir Protocols
SWC Registers
27. Banks 0 and 1 Common Control and Status Register Map
Type Name Value
Offset Type Name Value
29. Banks 0 and 1 Common Control and Status Registers
30. Bank 1 Ceir Wakeup Configuration and Control Registers
Bit Description Ceir Wakeup Range 1 Registers
Bank 1, Offset 0Ah IRWTR1L Register R/W
Ceir Pulse Change, Range 1, High Limit
Ceir Wakeup Range 2 Registers
ACCESS.bus Interface
Data Transactions
ABD ABC
AMD Geode SC1200/SC1201 Processor Data Book 121
Acknowledge ACK Cycle
ABD MSB
ABC ACK
Master Mode
Acknowledge After Every Byte Rule
Arbitration on the Bus
Addressing Transfer Formats
Sending the Address Byte
Master Transmit
Master Receive
Master Stop
Slave Mode
Configuration
ACB Registers
31. ACB Register Map
32. ACB Registers
MASTER. RO
Reserved Inten Interrupt Enable
Saen Slave Address Enable
EN Enable
Stop Stop
Legacy Functional Blocks
Parallel Port
33. Parallel Port Register Map for First Level Offset
34. Parallel Port Register Map for Second Level Offset
35. Parallel Port Bit Map for First Level Offset
36. Parallel Port Bit Map for Second Level Offset
130
Uart Functionality SP1 and SP2
Type Name
38. Bank Selection Encoding
39. Bank 1 Register Map
40. Bank 2 Register Map
41. Bank 3 Register Map
42. Bank 0 Bit Map
43. Bank 1 Bit Map
Register Bits
Register Bits Offset
44. Bank 2 Bit Map
45. Bank 3 Bit Map
134
3.1 IR/SP3 Mode Register Bank Overview
46. Bank 0 Register Map
IRCP/SP3 Register and Bit Maps
01h Register Throughout Offset 00h All Banks
47. Bank Selection Encoding
48. Bank 1 Register Map
49. Bank 2 Register Map
BSR Bits Bank Selected Functionality
50. Bank 3 Register Map
51. Bank 4 Register Map
52. Bank 5 Register Map
53. Bank 6 Register Map
54. Bank 7 Register Map
55. Bank 0 Bit Map
56. Bank 1 Bit Map
57. Bank 2 Bit Map
58. Bank 3 Bit Map
59. Bank 4 Bit Map
60. Bank 5 Bit Map
61. Bank 6 Bit Map
62. Bank 7 Bit Map
Feature List
Config
Integrated Audio
Video Processor Interface
Low Pin Count LPC Interface
Fast-PCI Interface to External PCI Bus
Pserial Interface
IDE Configuration Registers
PIO Mode
IDE Controller
Video Retrace Interrupt
Physical Region Descriptor Format
UltraDMA/33 Signal Definitions
UltraDMA/33 Mode
Stop
DMARDY# Strobe Ideiordy
Universal Serial Bus
Sub-ISA Bus Interface
IOCS0#/IOCS1#
Docw
Sub-ISA Support of Delayed PCI Transactions
Sub-ISA Bus Cycles
Fast-PCICLK
AD310 Read AD310 Write
5.4 I/O Recovery Delays
REQ# GNT#
FRAME# IRDY# TRDY# STOP# Bale ISA RD#, IOR#
Sub-ISA Bus Data Steering
ISA DMA
SD150
AD310
PCI and Sub-ISA Signal Cycle Multiplexing
Cycle Multiplexed PCI / Sub-ISA Balls
ROM Interface
PCI
FRAME# TRDY#, IRDY#
ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP#
DMA Controller
DMA Channels
DMA Transfer Modes
DMA Controller Registers
DMA Transfer Types
DMA Priority
Programmable Interval Timer
DMA Addressing Capability
DMA Page Registers and Extended Addressing
DMA Address Generation
PIC Interrupt Mapping
Programmable Interrupt Controller
Master
Mapping
PIC Interrupt Sequence
PIC I/O Registers
PIC Shadow Register
PCI Compatible Interrupts
Fast Keyboard Gate Address 20 and CPU Reset
Keyboard Support
7.1 I/O Port 092h System Control
7.2 I/O Port 061h System Control
Power Management Logic
Wakeup Events Capability
Power Planes Control Signals vs Sleep States
Power Planes vs. Sleep/Global States
Power Management Events
Power Button
Power Button Override
Thermal Monitoring
AMD Geode SC1200/SC1201 Processor Data Book 161
Power Management Programming
CPU Power Management
APM Support
Suspend Modulation
Volt Suspend
Save-to-Disk
AMD Geode SC1200/SC1201 Processor Data Book 163
Peripheral Power Management
Device Idle Timers and Traps
General Purpose Timers
Acpi Timer Register
Power Management SMI Status Reporting Registers
Module
F1BAR0+I/O
Device Power Management Programming Summary
Power Management Programming Summary
Located at F0 Index xxh Unless Otherwise Noted
F1BAR0+I/O
Gpio Interface
Integrated Audio
11. Physical Region Descriptor Format
Byte
Audio Data Buffer Reserved Size
Memory Region Base Address
PRD1 PRD2
PRD3
Codec Configuration/Control Registers
Codec Command Register
12.2 AC97 Codec Interface
Codec Gpio Status and Control Registers
Trap SMI Enable Register
VSA Technology Support Hardware
VSA Technology
Audio SMI Related Registers
Module Core Logic Module
IRQ Configuration Registers
Internal IRQ Enable Register
Internal IRQ Control Register
LPC Interface
12. Cycle Types
PCI Configuration Space and Access Methods
13. PCI Configuration Address Register 0CF8h
Register Descriptions
Ter’s reset values and page references where the bit for
Register Summary
Core Logic module. Included in the tables are the regis
Mats are found
Width Reset Reference F0 Index Bits
AMD Geode SC1200/SC1201 Processor Data Book 177
32579BCore Logic Module Register Summary
178
15. F0BAR0 Gpio Support Registers Summary
16. F0BAR1 LPC Support Registers Summary
F0BAR0+
F0BAR1+
18. F1BAR0 SMI Status Registers Summary
F1BAR0+
19. F1BAR1 Acpi Support Registers Summary
F1BAR1+
00h-03h Pcnt Processor Control Register
20h PM2CNT PM2 Control Register 00h 21h-FFh Not Used
Width Reset Reference F2 Index Bits
182
Width Reset Reference F3 Index Bits
21. F2BAR4 IDE Controller Support Registers Summary
22. F3 PCI Header Registers for Audio Support Summary
F2BAR4+
Width Reset
23. F3BAR0 Audio Support Registers Summary
F3BAR0+
184
Width Reset Reference F5 Index Bits
25. F5BAR0 I/O Control Support Registers Summary
F5BAR0+
AMD Geode SC1200/SC1201 Processor Data Book 185
26. Pciusb USB PCI Configuration Register Summary
Name Reset Value
Pciusb
Width Reference Index Bits
27. Usbbar USB Controller Registers Summary
USBBAR0
AMD Geode SC1200/SC1201 Processor Data Book 187
28. ISA Legacy I/O Register Summary
DMA Page Registers Table
188
Programmable Interval Timer Registers Table
Port Type Name Reference
Programmable Interrupt Controller Registers Table
Keyboard Controller Registers Table
Chipset Register Space
Bridge, GPIO, and LPC Registers Function
General Remarks
Core Logic Module Bridge, GPIO, and LPC Registers Function
Data Parity Detected. This bit is set when
Index 09h-0Bh
AMD Geode SC1200/SC1201 Processor Data Book 191
Index 0Eh PCI Header Type RO Reset Value 80h
Slave response
Index 0Fh PCI Bist Register RO
316 Gpio Base Address
PCI Subtractive Decode
AMD Geode SC1200/SC1201 Processor Data Book 193
Reset Control Register R/W Reset Value 01h
Index 42h
Index 43h
194
Index 45h
Index 46h
Index 47h
AMD Geode SC1200/SC1201 Processor Data Book 195
Reset Value 7Bh
PIT Software Reset
PIT Counter 1 Enable
PIT Counter 0 Enable
ROM/AT Logic Control Register R/W Reset Value 98h
Generate SMI on A20M# Toggle
AMD Geode SC1200/SC1201 Processor Data Book 197
Bit Description Index 54h-59h
Index 5Ah
Index 5Bh Decode Control Register 2 R/W
198
INTB# Ball C26 Target Interrupt
INTA# Ball D26 Target Interrupt
INTD# Ball AA2 Target Interrupt
INTC# Ball C9 Target Interrupt
150
Index 72h
200
Index 73h
Index 74h-75h
Index 76h
Chip Select 0 Positive Decode IOCS0#
Ing the upper 19 bits of the incoming PCI address AD3113
202
Power Management Enable Register 2 R/W Reset Value 00h
Timer expires Disable Enable
AMD Geode SC1200/SC1201 Processor Data Book 203
204
Power Management Enable Register 3 R/W Reset Value 00h
Keyboard/Mouse Access Trap
Parallel/Serial Access Trap
AMD Geode SC1200/SC1201 Processor Data Book 205
Floppy Disk Access Trap
Primary Hard Disk Access Trap
Index 83h Power Management Enable Register 4 R/W
206
Index 84h Second Level PME/SMI Status Mirror Register 1 RO
AMD Geode SC1200/SC1201 Processor Data Book 207
208
AMD Geode SC1200/SC1201 Processor Data Book 209
Index 88h General Purpose Timer 1 Count Register R/W
Reserved. Always reads
210
Re-trigger General Purpose Timer 1 on Floppy Disk Activity
Second Millisecond
AMD Geode SC1200/SC1201 Processor Data Book 211
Index 8Bh General Purpose Timer 2 Control Register R/W
Index 8Dh Video Speedup Timer Count Register R/W
212
Index 8Fh-92h
Index 93h
AMD Geode SC1200/SC1201 Processor Data Book 213
Index 9Ah-9Bh Floppy Disk Idle Timer Count Register R/W
Index 97h
Index 98h-99h
214
Index A6h-A7h Video Idle Timer Count Register R/W
Index A8h-A9h Video Overflow Count Register R/W
Index AEh CPU Suspend Command Register WO
Index AFh Suspend Notebook Command Register WO
Index B0h-B3h
Index B4h
Index B9h PIC Shadow Register RO
Index BAh PIT Shadow Register RO
AMD Geode SC1200/SC1201 Processor Data Book 217
Index BCh Clock Stop Control Register R/W Reset Value 00h
Reserved. Set to CPU Clock Stop
Index BDh-BFh
Index C0h-C3h
Bit Description Index CCh
Mask
Index CDh
Index CEh
Index EDh-F3h
Index F4h
Index F5h Second Level PME/SMI Status Register 2 RC
220
Index F6h Second Level PME/SMI Status Register 3 RC
AMD Geode SC1200/SC1201 Processor Data Book 221
Index F7h Second Level PME/SMI Status Register 4 RC
Reserved. Read as
222
Index F8h-FFh
30. F0BAR0+I/O Offset Gpio Configuration Registers
I/O mapped registers accessed through F0BAR0
Gpio Support Registers
Ration registers are located. -29gives the bit formats
Offset 14h-17h GPDI1 Gpio Data In 1 Register RO
F0BAR0+I/O Offset 18h is set, this edge generates a PME
316 Reserved. Must be set to
AMD Geode SC1200/SC1201 Processor Data Book 225
Bank
010010 = GPIO18 ball AG1 000011
010011 = GPIO19 ball C9 000100
010100 = GPIO20 balls A9, N31 000101
AMD Geode SC1200/SC1201 Processor Data Book 227
31. F0BAR1+I/O Offset LPC Interface Configuration Registers
LPC Support Registers
3121
Reserved. Set to
AMD Geode SC1200/SC1201 Processor Data Book 229
Polarity selection
230
Reserved Serial IRQ Enable
Serial IRQ Interface Mode
Number of IRQ Data Frames
AMD Geode SC1200/SC1201 Processor Data Book 231
232
LPC Game Port 1 Address Select. Selects I/O Port
LPC Game Port 0 Address Select. Selects I/O Port
LPC Floppy Disk Controller Address Select. Selects I/O Port
LPC Midi Address Select. Selects I/O Port
234
Bit
SMI Status and Acpi Registers Function
32. F1 PCI Header Registers for SMI Status and Acpi Support
33. F1BAR0+I/O Offset SMI Status Registers
SMI Status Support Registers
Core Logic Module SMI Status and Acpi Registers Function
AMD Geode SC1200/SC1201 Processor Data Book 237
Suspend Modulation Enable Mirror. Read to Clear
Offset 02h-03h Top Level PME/SMI Status Register RO/RC
238
AMD Geode SC1200/SC1201 Processor Data Book 239
Yes To enable SMI generation, set F0 Index 82h6 =
Yes To enable SMI generation, set F0 Index 82h5 =
Offset 04h-05h
240
AMD Geode SC1200/SC1201 Processor Data Book 241
Offset 0Ah-1Bh
These addresses should not be written Offset 1Ch-1Fh
242
Offset 24h-27h External SMI Register R/W
3124
AMD Geode SC1200/SC1201 Processor Data Book 243
244
AMD Geode SC1200/SC1201 Processor Data Book 245
Offset 28h-4Fh Not Used Reset Value 00h
50h-FFh
246
Offset 06h Smicmd OS/BIOS Requests Register R/W
34. F1BAR1+I/O Offset Acpi Support Registers
Acpi Support Registers
Clkval Clock Throttling Value. CPU duty cycle
SCI generation is always enabled
248
Offset 0Ah-0Bh PM1AEN PM1A PME/SCI Enable Register R/W
1511
Offset 0Ch-0Dh PM1ACNT PM1A Control Register R/W
1514 Reserved. Must be set to
250
AMD Geode SC1200/SC1201 Processor Data Book 251
252
Gpwio Control Register 1 R/W Reset Value 00h
Gpwio Control Register 2 R/W Reset Value 00h Reserved
Consumer Electronic Infrared
02h0
Gpwio Data Register R/W Reset Value 00h
Reserved Reset Value 00h 254
Reset Value 00000F00h
Bit Description Offset 18h-1Bh
Offset 21h-FFh
AMD Geode SC1200/SC1201 Processor Data Book 255
IDE Controller Registers Function
PIOMODE. PIO mode
Core Logic Module IDE Controller Registers Function
Bit Description Index 30h-3Fh
AMD Geode SC1200/SC1201 Processor Data Book 257
258
Bit Description Index 48h-4Bh
Index 50h-53h
Index 58h-5Bh
Index 60h-FFh
IDE Controller Support Registers
260
Offset 09h
Offset 0Ah
Offset 0Bh
Offset 0Ch-0Fh
37. F3 PCI Header Registers for Audio Configuration
Audio Registers Function
38. F3BAR0+Memory Offset Audio Configuration Registers
Audio Support Registers
Core Logic Module Audio Registers Function
Offset 04h-07h
264
AMD Geode SC1200/SC1201 Processor Data Book 265
These bits change only on a fast write to an even address
2316
266
AMD Geode SC1200/SC1201 Processor Data Book 267
268
Mask Internal IRQ15. Write Only
Mask Internal IRQ14. Write Only
Mask Internal IRQ11. Write Only
Mask Internal IRQ10. Write Only
Mask Internal IRQ4. Write Only
Mask Internal IRQ3. Write Only
Assert Masked Internal IRQ14
Reserved. Set to Assert Masked Internal IRQ12
Bit Description Assert Masked Internal IRQ1
AMD Geode SC1200/SC1201 Processor Data Book 271
Audio Bus Master 1 Command Register R/W Reset Value 00h
Offset 29h Audio Bus Master 1 SMI Status Register RC
Offset 2Ah-2Bh
Offset 2Ch-2Fh
Audio Bus Master 2 Command Register R/W Reset Value 00h
Offset 31h Audio Bus Master 2 SMI Status Register RC
Offset 32h-33h
Offset 34h-37h
Audio Bus Master 3 Command Register R/W Reset Value 00h
Offset 39h Audio Bus Master 3 SMI Status Register RC
Offset 3Ah-3Bh
Offset 3Ch-3Fh
Audio Bus Master 4 Command Register R/W Reset Value 00h
Offset 41h Audio Bus Master 4 SMI Status Register RC
Offset 42h-43h
Offset 44h-47h
Audio Bus Master 5 Command Register R/W Reset Value 00h
Offset 49h Audio Bus Master 5 SMI Status Register RC
Offset 4Ah-4Bh
Offset 4Ch-4Fh
Bus Expansion Interface Function
39. F5 PCI Header Registers for X-Bus Expansion
Bit Description Index 1Ch-1Fh
Index 20h-23h
Index 24h-27h
Index 28h-2Bh
Index 58h F5BARx Initialized Register R/W Reset Value 00h
Index 48h-4Bh F5BAR2 Mask Address Register R/W
Index 4Ch-4Fh F5BAR3 Mask Address Register R/W
Index 50h-53h F5BAR4 Mask Address Register R/W
Bit Description Index 64h-67h
Index 68h-FFh
280
40. F5BAR0+I/O Offset X-Bus Expansion Registers
Bus Expansion Support Registers
F5 Index 10h, Base Address Register 0 F5BAR0 set
Three USB transceivers. Default = 128
USB transceivers. Default =
Iotestporten Debug Test Port Enable
282
41. Pciusb USB PCI Configuration Registers
USB Controller Registers Pciusb
Core Logic Module USB Controller Registers Pciusb
AMD Geode SC1200/SC1201 Processor Data Book 283
Reset Value 08h
Index 0Dh Latency Timer Register R/W
Bit Description Index 06h-07h Status Register R/W
Reserved. Must be set to Index 08h
42. USBBAR+Memory Offset USB Controller Registers
32579BCore Logic Module USB Controller Registers Pciusb
286
HcInterruptEnable Register R/W Reset Value = 00000000h
OwnershipChangeEnable
RootHubStatusChangeEnable
FrameNumberOverflowEnable
Bit Description StartOfFrameEnable
Offset 20h-23h
Offset 24h-27h
Offset 28h-2Bh
Reset Value = 00000628h
Reset Value = 01000003h
Bit Description Offset 38h-3Bh HcFrameRemaining Register RO
Reserved. Read 0s
BalPower
Read LocalPowerStatusChange. Not supported. Always read
Offset 50h-53h HcRhStatus Register R/W
3018
HcRhPortStatus1 Register R/W Reset Value = 00000000h
Read PortResetStatus
Read PortSuspendStatus
AMD Geode SC1200/SC1201 Processor Data Book 291
Read PortEnableStatus
Read CurrentConnectStatus
292
AMD Geode SC1200/SC1201 Processor Data Book 293
Reserved Reset Value = xxh 294
AMD Geode SC1200/SC1201 Processor Data Book 295
ISA Legacy Register Space
43. DMA Channel Control Registers
Priority Mode
Timing Mode
Core Logic Module ISA Legacy Register Space
Write
Transfer Mode
Channel Number Mode Select
32579BCore Logic Module ISA Legacy Register Space
Bit Description Port 00Bh
Write DMA Command Register, Channels
Undefined
AMD Geode SC1200/SC1201 Processor Data Book 299
Bit Description Port 0D2h
Port 0D4h
Port 0D6h
Port 0D8h
44. DMA Page Registers
45. Programmable Interval Timer Registers
Current Counter Mode BCD Mode
Bit Description Port 042h Write
Counter Value Read
Port 043h R/W
46. Programmable Interrupt Controller Registers
Poll Command
Register Read Mode
Bit Description IRQ1 / IRQ9 Mask
IRQ0 / IRQ8 Mask
Interrupt Service Register IRQ7 / IRQ15 In-Service
IRQ6 / IRQ14 In-Service
IRQ5 / IRQ13 In-Service
IRQ4 / IRQ12 In-Service
47. Keyboard Controller Registers
48. Real-Time Clock Registers
49. Miscellaneous Registers
AMD Geode SC1200/SC1201 Processor Data Book 309
310
General Features
Video Input Port VIP Interface
Hardware Video Acceleration
Graphics-Video Overlay and Blending
Display Modes
Video Input Port
VIP
Tvout
Functional Description
Video Support
VBI Support
Video Processor Module
Active Video
Video Input Port VIP
Direct Mode and Capture Mode Configurations
Bob
Address not changed during runtime
AMD Geode SC1200/SC1201 Processor Data Book 317
Weave
Capture VBI Mode
Ping-pongs between the two buffers during runtime
AMD Geode SC1200/SC1201 Processor Data Book 319
Video Block
Video Input Formatter
Line Buffer
320
Horizontal Downscaler with 4-Tap Filtering
Filtering
Horizontal Downscaler
Maintaining Aspect Ratio
Line Buffers
Formatter
2.5 2-Tap Vertical and Horizontal Upscalers
Ai,j Ai,j+1 Ai+1,jAi+1,j+1
Mixer/Blender Block
CSC
RGB
RAM
Valid Mixing/Blending Configurations
Filter2 Bit Mode Comment
Flicker
324
YUV to RGB CSC in Video Data Path
Gamma Correction
RGB to YUV CSC
3.4 1/2 Y Flicker Filter
Graphics Window
Video Window
Cursor Window
Alpha Windows
Truth Table for Alpha Blending
Mixing/Blending Operation
Color
CHROMASEL1
328
Flicker Filter, Interlaced Video YUV Mixing/Blending Mode
Tvout Block
Flicker Filter and Scan Rate Conversion
Vesa
Vesa DDSC2B and Dpms Support
Integrated DACs
Power Sequence
TFT Interface
HSYNC, VSYNC, TFTDE, Tftdck
T1 is a programmable multiple of frame time T0+T1
Divider Phase Charge Loop
Integrated PLL
Compare Pump Filter Divider Out
332
F4BAR0 Video Processor Configuration Registers Summary
F4 PCI Header Registers for Video Processor Support Summary
F4BAR0+
32579BVideo Processor Module Register Summary
334
Name Value Tvout Configuration Registers
F4BAR2 VIP Support Registers Summary
Encoder Registers
F4BAR2+
Reset Value 0504h
Reset Value 030000h
Video Processor Registers Function
3112 VIP Base Address 110 Address Range. Read Only
Video Processor Module Video Processor Registers Function
Index 3Eh-FFh Reserved
AMD Geode SC1200/SC1201 Processor Data Book 337
Video Configuration Register R/W Reset Value 00000000h
EN42X Enable 42x Format. Allows format selection
Video Processor Support Registers F4BAR0
To 0 or 1 should be written with a value that is read
Offset 04h-07h Display Configuration Register R/W
Tions of the power sequence control lines 1614
3028
Ddcsdaout DDC Output Data. DDC data bit for output
Offset 08h-0Bh Video X Position Register R/W
340
Bit Description 100
AMD Geode SC1200/SC1201 Processor Data Book 341
Reset Value 00001400h
12 PLL2PWREN PLL2 Power-Down Enable
Bit Description Offset 1Ch-1Fh
Block Offset 20h-23h
DTS Downscale Type Select
Offset 40h-43h Video Downscaler Coefficient Register R/W
FLTCO4 Filter Coefficient 4. For the tap-4 filter
FLTCO3 Filter Coefficient 3. For the tap-3 filter
Reserved Signen Signature Enable
Reset Value 0000xxxxh
Reset Value 00060000h
Bit Description Offset 44h-47h CRC Signature Register R/W
100 i.e., shift one line otherwise, leave at
AMD Geode SC1200/SC1201 Processor Data Book 345
Bit Description Offset 50h-53h
Offset 54h-57h
Offset 60h-63h Alpha Window 1 X Position Register R/W
346
3118
Decremented until it is reloaded via bit 17 Loadalpha
AMD Geode SC1200/SC1201 Processor Data Book 347
348
Offset 90h-93h
Offset 94h-97h
Offset 400h-403h
Video Fifo Underflow Empty
Video Fifo OverFlow Full
VBI Fifo Underflow Empty
VBI Fifo Overflow Full
Upscale horizontally VBI data by
Genlocktouten GenLock Timeout Enable
Bit Description Offset 414h-417h
3120 Reserved 190
Port Offset 41Ch-41Fh
Ctgenlocken Enable Continuous GenLock Function
Sggenlocken Enable a Single GenLock Function
Offset 424h-427h
3121 Reserved 200
Bit Description Offset 80Ch-80Fh
Offset 810h-813h
Horintp Horizontal Interpolation
Fieldinvr Field Invert
Offset 81Ch-81Fh
Offset C00h-C03h
2920
AMD Geode SC1200/SC1201 Processor Data Book 355
TV DAC Mode Bits Ball No
A23 Mode
Offset C08h-C0Bh
D24 A24
Offset C24h-C27h
3114
Offset C28h-C2Bh
AMD Geode SC1200/SC1201 Processor Data Book 357
Reset Value 00000020h
Reset Value 00000004h
Bit Description Offset C2Ch-C2Fh
Offset C50h-C53h
10. F4BAR2+Memory Offset VIP Configuration Registers
VIP Support Registers F4BAR2
All other decodes Reserved
AMD Geode SC1200/SC1201 Processor Data Book 359
Capture Store to Memory VBI Data
Capture Store to Memory Video Data
Reserved.Read Only Current Field. Read Only
2322
Video Data Capture Active. Read Only
Reserved. Read Only Run Status. Read Only
Offset 14h-17h
Offset 24h-27h Video Data Even Base Register R/W
3116 Reserved 150
Offset 2Ch-3Fh
Offset 44h-47h VBI Data Even Base Register R/W
Offset 48h-4Bh VBI Data Pitch Register R/W
Jtag Mode Instruction Support
Testability Jtag
Mandatory Instruction Support
Optional Instruction Support
364
General Specifications
Power/Ground Connections and Decoupling
Electro Static Discharge ESD
Absolute Maximum Ratings
Symbol Parameter Min Typ Max Unit Comments
Operating Conditions
366
Power Planes of External Interface Signals
Power Plane Signal Names VCC Balls VSS Balls
Power State Parameter Definitions
DC Current
DC Characteristics for On State
DC Characteristics for Active Idle, Sleep, and Off States
Symbol Parameter Note Min Typ Max Unit Comments
Symbol Parameter Min Typ Max Unit Comment
Ball Capacitance and Inductance
Pull-Up and Pull-Down Resistors
Balls with PU/PD Resistors
VIO
External PU or PD resistor
DC Characteristics
Symbol Description Reference
Wire
10. Buffer Types
Inab DC Characteristics
Inbtn DC Characteristics
Inpci DC Characteristics
Instrp DC Characteristics
INT DC Characteristics
Ints DC Characteristics
INTS1 DC Characteristics
Inusb DC Characteristics
ODn DC Characteristics
Odpci DC Characteristics
Op/n DC Characteristics
Opci DC Characteristics
Ousb DC Characteristics
AC Characteristics
11. Default Levels for Measurement Switching Parameters
Symbol Parameter Value
CLK
Memory Controller Interface
Outputs
Inputs
32579BElectrical Specifications
12. Memory Controller Timing Parameters
SDCLK30, Sdclkout high time
13.5
T1, t2, t3 t10
SDCLK30 Control Output, MA120
BA10, MD630
MD630 Data Valid Read Data
Vpckin Vref
14. Video Output Port Timing Parameters
CRT and TFT Interface
15. TFT Timing Parameters
Symbol Parameter Note Min Max Unit Comments
16. CRT Vesa Compatible DAC RED, GREEN, and Blue Outputs
RES
IRE
LSB DNL
LSB Tvref
ACCESS.bus Interface
18. ACCESS.bus Input Timing Parameters
19. ACCESS.bus Output Timing Parameters
AB1D AB2D
AB1C AB2C
AB1D AB2D AB1C AB2C
AB1D AB2D AB1C
AMD Geode SC1200/SC1201 Processor Data Book 387
20. PCI AC Specifications
PCI Bus
64VIO
Equation a Equation B
21. PCI Clock Parameters
Pciclk 0.4 V IO
22. PCI Timing Parameters
Symbol Value Unit Comments
23. Measurement Condition Parameters
Measurement and Test Conditions
Power
Signals
Input Valid
Ms typ
Symbol Parameter Bits Type Comments
Sub-ISA Interface
24. Sub-ISA Timing Parameters
Bus Width Min
Bus Width Min Max Symbol Parameter Bits Type Comments
MEMR#/DOCR#/IOR#
ROMCS#/DOCCS#
IOR#/RD#/TRDE#
MEMR#/DOCR#
IOW#/WR# MEMW#/DOCW#
DOCCS#/ROMCS#
IOCS10#
IOW#/WR# MEMW#/DOCW# TRDE#
D150
LPC Interface 25. LPC and Serirq
IDE signals fall time from 0.9V IO to 0.1V IO = 40 pF
IDE signals rise time from 0.1V IO to 0.9V IO = 40 pF
IDE Interface Timing 26. IDE General Timing Parameters
IDERST# pulse width
Mode Symbol Parameter Unit Comments
27. IDE Register Transfer to/from Device Timing Parameters
Cycle time min
Width 8-bit min
Addr valid1
IDEIOR0# IDEIOW0# Write IDEDATA70
Read IDEDATA70
IDEIORDY0 2,3
28. IDE PIO Data Transfer to/from Device Timing Parameters
165 125 100
402
IDEIOR0# IDEIOW0# Write IDEDATA150
Read IDEDATA150
AMD Geode SC1200/SC1201 Processor Data Book 403
29. IDE Multiword DMA Data Transfer Timing Parameters
IDECS10#
IDEDREQ0 IDEDACK0# IDEIOR0# IDEIOW0#
AMD Geode SC1200/SC1201 Processor Data Book 405
Mode Symbol Parameter Min Max Unit Comments
30. IDE UltraDMA Data Burst Timing Parameters
406
IDEREQ0
STOP0
IDEIOR0# HDMARDY0#
IDEIRDY0 DSTROBE0
IDEIRDY0 DSTROBE0 at device
IDEDATA150 at device IDEIRDY0 DSTROBE0 at host
IDEDATA150 at host
408
IDEDREQ0 device IDEDACK0# host
IDEIOW0#STOP0# host
IDEIOR0#HDMARDY0#
AMD Geode SC1200/SC1201 Processor Data Book 409
IDEDREQ0 device
IDEIOW0# STOP0#
410
IDEIOW0# STOP0# host IDEIOR0# HDMARDY0# host
IDEIRDY0 DSTROBE0 device IDEDATA150 device
IDECS01#
IDEADDR20
DevicetUI IDEDACK0# host
IDEIOW0# STOP0# host
IDEIORDY0 DDMARDY0 device
IDEIOR0# HSTROBE0# host
HSTROBE0#
At host
IDEDATA150 At host IDEIOR0# HSTROBE0# at device
IDEDATA150 at device
IDEDREQ0 device IDEDACK0# host IDEIOW0# STOP0# host
IDEIORDY0# DDMARDY0#
IDEIOR0# HSTROBE0#
414
IDEIORDY0# DDMARDY0# device
IDEDATA150 host IDEADDR20 IDECS01#
IDEDACK0# host
AMD Geode SC1200/SC1201 Processor Data Book 415
IDEDREQ0 device IDEDACK0 host IDEIOW0# STOP0# host
IDEDATA150 host IDECS01# IDEADDR20
416
Universal Serial Bus USB 31. USB Timing Parameters
Full Speed Receiver EOP Width Note
Low Speed Source Note
Source EOP width
Host upstream
Receiver data jitter tolerance for paired
Low Speed Receiver EOP Width Note
Rise Time Fall Time
Differential Data Lines
Differential Data Lines Crossover Points 2.0
Consecutive Transitions
Differential Data to SE0 Skew
Data Crossover Level
EOP Width
Differential Crossover Points Data Lines
Modulation signal period
TCPN + Transmitter Sharp-IR and Consumer Remote Control
SIR signal pulse width
Setting of the Rxhsc bit bit 5 of the Rccfg register
Fast IR Port Timing 33. Fast IR Port Timing Parameters
MIR
FIR
Busy ACK#
STB#
Symbol Parameter Min
35. Enhanced Parallel Port Timing Parameters
Unit Comments
36. ECP Forward Mode Timing Parameters
Extended Capabilities Port ECP Timing
AFD#
Busy
37. ECP Reverse Mode Timing Parameters
BUSY#
Audio Interface Timing AC97 38. AC Reset Timing Parameters
AC97RST# inactive to Bitclk 162.8 Startup delay
Sync inactive to Bitclk startup 162.8 Delay
AC97RST# active low pulse width
40. AC97 Clocks Parameters
AC97CLK Vold
41. AC97 I/O Timing Parameters
SDATAOUT/SYNC SDATAIN, SDATAIN2
42. AC97 Signal Rise and Fall Timing Parameters
43. AC97 Low Power Mode Timing Parameters
End of Slot 2 to Bitclk Sdatain low
Slot
Bitclk Sdataout
Power Management
Power management event to ONCTL# Assertion
44. PWRBTN# Timing Parameters
ONCTL# PWRBTN#
PWRBTN# ONTCL# PWRCNT21 POR#
POR# 32KHZ
434
TDI, TMS setup time
Non-test inputs setup time
Jtag Interface 48. Jtag Timing Parameters
TDI, TMS hold time
Output Signals
Input Signals
TDI TMS TDO
436
Thermal Characteristics
ΘJC ×C/W
Case-to-Ambient Thermal Resistance Example @ 85C
Heatsink Considerations
Example
Assume P max = 5W and TA max = 40C Therefore
Assume P max = 9W and TA max = 40C Therefore
Physical Dimensions
Package Specifications
AMD Geode SC1200/SC1201 Processor Data Book 439
BGU481 Package Bottom View
440
Order Information
Macrovision Product Notice
Ordering Part Number Core Frequency
MHz
Data Book Revision History
Table A-1. Revision History
Revision # Revisions / Comments
