ACCESS.bus Interface | AMD SC1201, SC1200 manual

Electrical Specifications

32579B

9.3.5ACCESS.bus Interface

The following tables describe the timing for the ACCESS.bus signals.

Notes: 1) All ACCESS.bus timing is not 100% tested.

2) In this table tCLK = 1/24MHz = 41.7 ns.

Table 9-18. ACCESS.bus Input Timing Parameters

Symbol	Parameter	Min	Max	Unit	Comments

tBUFi	Bus free time between	tSCLhigho
	Stop and Start condition

tCSTOsi	AB1C/AB2C setup time	8 * tCLK - tSCLri			Before Stop condition
tCSTRhi	AB1C/AB2C hold time	8 * tCLK - tSCLri			After Start condition
tCSTRsi	AB1C/AB2C setup time	8 * tCLK - tSCLri			Before Start condition
tDHCsi	Data high setup time	2 * tCLK			Before AB1C/AB2C rising edge
tDLCsi	Data low setup time	2 * tCLK			Before AB1C/AB2C rising edge
tSCLfi	AB1D/AB2D fall time		300	ns
tSCLri	AB1D/AB2D rise time		1	μs
tSCLlowi	AB1C/AB2C low time	16 * tCLK			After AB1C/AB2C falling edge
tSCLhighi	AB1C/AB2C high time	16 * tCLK			After AB1C/AB2C rising edge
tSDAfi	AB1D/AB2D fall time		300	ns
tSDAri	AB1D/AB2D rise time		1	μs
tSDAhi	AB1D/AB2D hold time	0			After AB1C/AB2C falling edge
tSDAsi	AB1D/AB2D setup time	2 * tCLK			Before AB1C/AB2C rising edge

Table 9-19. ACCESS.bus Output Timing Parameters

Symbol	Parameter	Min	Max	Unit	Comments

tSCLhigho	AB1C/AB2C high time	K * tCLK - 1 μs			After AB1C/AB2C rising edge,
					Note 1

tSCLlowo	AB1C/AB2C low time	K * tCLK - 1 μs			After AB1C/AB2C falling edge
tBUFo	Bus free time between	tSCLhigho	1	μs	Note 2
	Stop and Start condition

tCSTOso	AB1C/AB2C setup time	tSCLhigho	1	μs	Before Stop condition, Note 2
tCSTRho	AB1C/AB2C hold time	tSCLhigho	1	μs	After Start condition, Note 2
tCSTRso	AB1C/AB2C setup time	tSCLhigho	1	μs	Before Start condition, Note 2
tDHCso	Data high setup time	tSCLhigho - tSDAro	1	μs	Before AB1C/AB2C rising
					edge, Note 2

tDLCso	Data low setup time	tSCLhigho - tSDAfo	1	μs	Before AB1C/AB2C rising
					edge, Note 2

tSCLfo	AB1D/AB2D signal fall		300	ns
	time

tSCLro	AB1D/AB2D signal rise		1	μs
	time


AMD Geode™ SC1200/SC1201 Processor Data Book					385

Image 385

AMD SC1201, SC1200 manual ACCESS.bus Interface, ACCESS.bus Input Timing Parameters, ACCESS.bus Output Timing Parameters

Contents

AMD Geode SC1200/SC1201 Processor Data Book Publication ID 32579B Contacts Trademarks Advanced Micro Devices, Inc. All rights reserved Contents Package Specifications Electrical SpecificationsCore Logic Module Video Processor Module Typical Battery Configuration Power Supply ConnectionsTypical Battery Current Normal Operation Mode ACCESS.bus Data Transaction USB Data Signal Rise and Fall Timing Diagram 419 Multiword DMA Data Transfer Timing Diagram 405USB EOP Width Timing Diagram 420 Fast IR Timing MIR and FIR Diagram 422 425 424426 427 32579B Serial Ports 1 and 2 Configuration Register IRCP/SP3 Configuration RegisterACB1 and ACB2 Configuration Register Parallel Port Configuration Register 119 Banks 0 and 1 Common Control and Status Registers 118166 167 F0BAR0+I/O Offset Gpio Configuration Registers Pciusb USB PCI Configuration Register SummaryF2BAR4+I/O Offset IDE Controller Configuration Registers F3 PCI Header Registers for Audio Configuration 400 384402 404 Video Processor General DescriptionCore Logic SuperI/O General Features FeaturesGX1 Processor Module Video Processor Module Core Logic Module Other FeaturesNand Eeprom SuperI/O Module 32579B Memory Controller GX1 ModuleArchitecture Overview 32579B SC1200/SC1201 Processor Memory Controller Register Summary Width Memory Offset Bits Type Name/Function Reset ValueSC1200/SC1201 Processor Memory Controller Registers MCMEMCNTRL2 R/W Mcbankcfg R/W Bit Description GXBASE+8408h-840BhRsvd Reserved. Write as 0070h Rsvd Reserved. Write as GXBASE+840Ch-840Fh Mcdradd R/W Mcgbaseadd R/WMcdracc R/W Display Fast-PCI Bus1 GX1 Module Interface Video Input Port Reset Logic Clock, Timers, and Reset LogicPower-On Reset System Reset 32579B AMD Geode Signal Definitions 32579BSC1200/SC1201 Processor Jtag Interface USB Mnemonic Definition Signal Definitions Legend SC1200/SC1201 BGU481 Ball Assignment Sorted by Ball Number Configuration REQ0# GNT0# GPIO7 AFD#/DSTRB# PAR GPIO12 FTRDY# AC1 IDEDATA1 Buffer1 Power Signal Name Ball Buffer Power Signal Name Signal Name Ball No BGU481 Ball Assignment Sorted Alphabetically by Signal Name FC/BE0# D21 F30C11 FC/BE1# B17 MD24 MD23MD25 AC28 MD26 AC29 N13, N14, N18 C24A2, A30, B2, B13 F31 Strap Options Nominal External PU/PD Strap SettingsStrap Options Two-Signal/Group Multiplexing Multiplexing ConfigurationDefault Alternate Ball No Signal Configuration TFT, CRT, PCI, GPIO, System Internal Test ACCESS.busAC97 Fpci Monitoring Three-Signal/Group Multiplexing Gpio UART2 IDE2 Four-Signal/Group Multiplexing Signal Name Ball No Type Description Mux Signal DescriptionsMaximum Core Clock Multiplier. These strap signals Boot ROM is 16 Bits Wide. This strap signal enables Column Address Strobe. RAS#, CAS#, WE# and CKE Memory Interface Signals Video Port Interface Signals 4 CRT/TFT Interface Signals Digital RGB Data to TFT Super Video Chrominance. S-Video chrominance sig TV Interface SignalsCurrent Compensation for TV DAC. a 0.1 µF to 1.2 µF PCI Bus Interface Signals ACCESS.bus Interface Signals INTB# INTA#INTC# INTD# AA2 LOCK# STOP#DEVSEL# BHE# SERR# PERR#REQ1# REQ0# Sub-ISA Interface Signals Low Pin Count LPC Bus Interface Signals IDE Interface Signals Serial Ports UARTs Interface Signals Universal Serial Bus USB Interface Signals Parallel Port Interface Signals Fast Infrared IR Port Interface Signals Power Management Interface Signals 15 AC97 Audio Interface SignalsGeneral Purpose Wakeup I/Os. These signals each Serial Bus Synchronization. This bit is asserted to syn PWRBTN# AH5 Suspend Power Plane Control 1 and 2. Control signalPWRCNT1 AK6 PWRCNT2 AL7 Gpio Interface Signals Jtag Interface Signals Debug Monitoring Interface SignalsFast-PCI Bus Monitoring Signals. When enabled, this System Management Interrupt. This is the input to PLL6, PLL5 and PLL2 Bypass. These signals are used Test and Measurement Interface SignalsMemory Internal Test Signals. These signals are used Thermal Diode Positive / Negative. These signals are for Power and Ground Connections1 General Configuration Block Register Summary Configuration Block AddressesGeneral Configuration Block 32579B Width Offset Bits Other Signal Add’l Dependencies Ball # Internal Test Signals Name Add’l DependenciesPMR27 Fpcimon Ball # IDE Signals CRT, Gpio and TFT Signals Name General Configuration Block Name Add’l Dependencies PP/ACB1/FPCI TFT/VOP Ball # Gpio Signals LPC Signals Name Add’l Dependencies Reserved 32579BGeneral Configuration Block General Configuration Block Offset 38h Interrupt Selection Register Intsel R/W Offset 3Eh-3Fh Configuration Base Address Register CBA ROOffset 3Dh Revision Register REV RO Functional Description Watchdog Timer Watchdog Interrupt Watchdog Registers3describes the Watchdog registers Usage Hints High-Resolution Timer Registers High-Resolution TimerWatchdog Status Register Wdsts R/WC Reset Value 00h Offset 05h-07h Tmclksel Timer Clock Select Reset Value xxxxxxxxhTmen Timer Interrupt Enable Bit Description Offset 08h-0Bh Clock Generators and PLLs Crystal Oscillator Circuit Components 1 27 MHz Crystal OscillatorComponent Parameters Values Tolerance Internal Fast-PCI Clock 2 GX1 Module Core ClockCore Clock Frequency Strapped Core Clock Frequency Core Logic Module Clocks SuperI/O ClocksVideo Processor Clocks Clock Registers Clock Generator ConfigurationClock generator and PLL registers are described in Table Reserved. Must be set to 1110 151433.3 MHz 66.7 MHz ISA Outstanding FeaturesAB1C AB1D AB2C AB2D Parallel Port PC98 and Acpi CompliantSerial Port Serial Port 3 / Infrared IR Communication Port Signals AccessInternal Internal Signals Module Architecture SIO Configuration Options Configuration Structure / AccessIndex-Data Register Pair LDN Assignments Address Decoding Default Configuration Setup SIO Control and Configuration Registers Standard Configuration RegistersLogical Device Control and Configuration Registers Standard Logical Device Configuration Registers Standard Configuration Registers 32579BSuperI/O Module Index F0h-FEh Logical Device Configuration R/WDMA Channel Select 1 R/W SIO Control and Configuration Register Map SIO Control and Configuration RegistersIndex Type Name Power Rail Reset Value SID. SIO ID Relevant RTC Configuration Registers Logical Device Control and Configuration RTC Configuration Registers LDN 01h System Wakeup Control Relevant SWC RegistersBase Address MSB register Relevant IRCP/SP3 Registers 10. IRCP/SP3 Configuration Register Serial Ports 1 and 2 Configuration register 12. Serial Ports 1 and 2 Configuration Register11. Relevant Serial Ports 1 and 2 Registers LDN 03h and 08h Serial Ports 1 LDN 05h and 06h ACCESS.bus Ports 1 14. ACB1 and ACB2 Configuration RegisterACB1 and ACB2 Configuration register 13. Relevant ACB1 and ACB2 Registers 15. Relevant Parallel Port Registers 16. Parallel Port Configuration Register Real-Time Clock RTC X32I External X32O Battery = 0.1 μFBus Interface RTC Clock Generation 17. Crystal Oscillator Circuit Components External Elements Signal ParametersOscillator Startup External Oscillator Timekeeping Data Format AlarmsDaylight Saving Leap Years Power Supply 18. System Power States Interrupt Handling Battery-Backed RAMs and Registers110 19. RTC Register Map RTC Registers20. RTC Registers Index Type Name Index 04h Hours Register HOR R/W Index 05h Hours Alarm Register Hora R/WCRD is 112 Index 0Ch RTC Control Register C CRC RO Index Programmable Month Alarm Register Mona R/WIndex Programmable Century Register CEN R/W AMD Geode SC1200/SC1201 Processor Data Book 113 22. Periodic Interrupt Rate Encoding 21. Divider Chain Control / Test Selection23. BCD and Binary Formats Parameter BCD Format Binary Format 00h 7Fh Battery-backed general-purpose Byte RAM 0Eh 7Fh Battery-backed general-purpose Byte RAMRTC General-Purpose RAM Map 24. Standard RAM Map 25. Extended RAM Map Event Detection System Wakeup Control SWC26. Time Range Limits for Ceir Protocols 27. Banks 0 and 1 Common Control and Status Register Map SWC RegistersType Name Value Offset Type Name Value 29. Banks 0 and 1 Common Control and Status Registers 30. Bank 1 Ceir Wakeup Configuration and Control Registers Bank 1, Offset 0Ah IRWTR1L Register R/W Bit Description Ceir Wakeup Range 1 RegistersCeir Pulse Change, Range 1, High Limit Ceir Wakeup Range 2 Registers Data Transactions ACCESS.bus InterfaceABD ABC AMD Geode SC1200/SC1201 Processor Data Book 121 ABD MSB Acknowledge ACK CycleABC ACK Acknowledge After Every Byte Rule Master ModeArbitration on the Bus Addressing Transfer Formats Master Transmit Sending the Address ByteMaster Receive Master Stop Configuration Slave Mode 31. ACB Register Map ACB Registers32. ACB Registers MASTER. RO Saen Slave Address Enable Reserved Inten Interrupt EnableEN Enable Stop Stop Parallel Port Legacy Functional Blocks33. Parallel Port Register Map for First Level Offset 34. Parallel Port Register Map for Second Level Offset 36. Parallel Port Bit Map for Second Level Offset 35. Parallel Port Bit Map for First Level Offset130 Type Name Uart Functionality SP1 and SP2 39. Bank 1 Register Map 38. Bank Selection Encoding40. Bank 2 Register Map 41. Bank 3 Register Map 43. Bank 1 Bit Map 42. Bank 0 Bit MapRegister Bits Register Bits Offset 45. Bank 3 Bit Map 44. Bank 2 Bit Map134 46. Bank 0 Register Map 3.1 IR/SP3 Mode Register Bank OverviewIRCP/SP3 Register and Bit Maps 01h Register Throughout Offset 00h All Banks 48. Bank 1 Register Map 47. Bank Selection Encoding49. Bank 2 Register Map BSR Bits Bank Selected Functionality 51. Bank 4 Register Map 50. Bank 3 Register Map52. Bank 5 Register Map 54. Bank 7 Register Map 53. Bank 6 Register Map55. Bank 0 Bit Map 57. Bank 2 Bit Map 56. Bank 1 Bit Map58. Bank 3 Bit Map 59. Bank 4 Bit Map 61. Bank 6 Bit Map 60. Bank 5 Bit Map62. Bank 7 Bit Map Feature List Integrated Audio ConfigVideo Processor Interface Low Pin Count LPC Interface Pserial Interface Fast-PCI Interface to External PCI Bus PIO Mode IDE Configuration RegistersIDE Controller Video Retrace Interrupt Physical Region Descriptor Format UltraDMA/33 Mode UltraDMA/33 Signal DefinitionsStop DMARDY# Strobe Ideiordy Sub-ISA Bus Interface Universal Serial BusIOCS0#/IOCS1# Docw Sub-ISA Bus Cycles Sub-ISA Support of Delayed PCI TransactionsFast-PCICLK AD310 Read AD310 Write REQ# GNT# 5.4 I/O Recovery DelaysFRAME# IRDY# TRDY# STOP# Bale ISA RD#, IOR# Sub-ISA Bus Data Steering SD150 ISA DMAAD310 Cycle Multiplexed PCI / Sub-ISA Balls PCI and Sub-ISA Signal Cycle MultiplexingROM Interface PCI ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP# FRAME# TRDY#, IRDY#DMA Controller DMA Channels DMA Controller Registers DMA Transfer ModesDMA Transfer Types DMA Priority DMA Addressing Capability Programmable Interval TimerDMA Page Registers and Extended Addressing DMA Address Generation Programmable Interrupt Controller PIC Interrupt MappingMaster Mapping PIC I/O Registers PIC Interrupt SequencePIC Shadow Register PCI Compatible Interrupts Keyboard Support Fast Keyboard Gate Address 20 and CPU Reset7.1 I/O Port 092h System Control 7.2 I/O Port 061h System Control Power Management Logic Wakeup Events Capability Power Planes vs. Sleep/Global States Power Planes Control Signals vs Sleep StatesPower Management Events Power Button Override Power ButtonThermal Monitoring AMD Geode SC1200/SC1201 Processor Data Book 161 CPU Power Management Power Management ProgrammingAPM Support Suspend Modulation Save-to-Disk Volt SuspendAMD Geode SC1200/SC1201 Processor Data Book 163 Device Idle Timers and Traps Peripheral Power ManagementGeneral Purpose Timers Acpi Timer Register Module Power Management SMI Status Reporting RegistersF1BAR0+I/O Power Management Programming Summary Device Power Management Programming SummaryLocated at F0 Index xxh Unless Otherwise Noted F1BAR0+I/O Integrated Audio Gpio Interface Byte 11. Physical Region Descriptor FormatAudio Data Buffer Reserved Size Memory Region Base Address PRD3 PRD1 PRD2 Codec Command Register Codec Configuration/Control Registers12.2 AC97 Codec Interface Codec Gpio Status and Control Registers VSA Technology Support Hardware Trap SMI Enable RegisterVSA Technology Audio SMI Related Registers Module Core Logic Module Internal IRQ Enable Register IRQ Configuration RegistersInternal IRQ Control Register LPC Interface 12. Cycle Types 13. PCI Configuration Address Register 0CF8h PCI Configuration Space and Access MethodsRegister Descriptions Register Summary Ter’s reset values and page references where the bit forCore Logic module. Included in the tables are the regis Mats are found AMD Geode SC1200/SC1201 Processor Data Book 177 Width Reset Reference F0 Index Bits 178 32579BCore Logic Module Register Summary 16. F0BAR1 LPC Support Registers Summary 15. F0BAR0 Gpio Support Registers SummaryF0BAR0+ F0BAR1+ F1BAR0+ 18. F1BAR0 SMI Status Registers Summary F1BAR1+ 19. F1BAR1 Acpi Support Registers Summary00h-03h Pcnt Processor Control Register 20h PM2CNT PM2 Control Register 00h 21h-FFh Not Used 182 Width Reset Reference F2 Index Bits 21. F2BAR4 IDE Controller Support Registers Summary Width Reset Reference F3 Index Bits22. F3 PCI Header Registers for Audio Support Summary F2BAR4+ 23. F3BAR0 Audio Support Registers Summary Width ResetF3BAR0+ 184 25. F5BAR0 I/O Control Support Registers Summary Width Reset Reference F5 Index BitsF5BAR0+ AMD Geode SC1200/SC1201 Processor Data Book 185 Name Reset Value 26. Pciusb USB PCI Configuration Register SummaryPciusb Width Reference Index Bits USBBAR0 27. Usbbar USB Controller Registers SummaryAMD Geode SC1200/SC1201 Processor Data Book 187 DMA Page Registers Table 28. ISA Legacy I/O Register Summary188 Port Type Name Reference Programmable Interval Timer Registers TableProgrammable Interrupt Controller Registers Table Keyboard Controller Registers Table Bridge, GPIO, and LPC Registers Function Chipset Register SpaceGeneral Remarks Data Parity Detected. This bit is set when Core Logic Module Bridge, GPIO, and LPC Registers FunctionIndex 09h-0Bh AMD Geode SC1200/SC1201 Processor Data Book 191 Slave response Index 0Eh PCI Header Type RO Reset Value 80hIndex 0Fh PCI Bist Register RO 316 Gpio Base Address AMD Geode SC1200/SC1201 Processor Data Book 193 PCI Subtractive Decode Index 42h Reset Control Register R/W Reset Value 01hIndex 43h 194 Index 46h Index 45hIndex 47h AMD Geode SC1200/SC1201 Processor Data Book 195 PIT Software Reset Reset Value 7BhPIT Counter 1 Enable PIT Counter 0 Enable Generate SMI on A20M# Toggle ROM/AT Logic Control Register R/W Reset Value 98hAMD Geode SC1200/SC1201 Processor Data Book 197 Index 5Ah Bit Description Index 54h-59hIndex 5Bh Decode Control Register 2 R/W 198 INTA# Ball D26 Target Interrupt INTB# Ball C26 Target InterruptINTD# Ball AA2 Target Interrupt INTC# Ball C9 Target Interrupt Index 72h 150200 Index 74h-75h Index 73hIndex 76h Chip Select 0 Positive Decode IOCS0# 202 Ing the upper 19 bits of the incoming PCI address AD3113 Timer expires Disable Enable Power Management Enable Register 2 R/W Reset Value 00hAMD Geode SC1200/SC1201 Processor Data Book 203 204 Keyboard/Mouse Access Trap Power Management Enable Register 3 R/W Reset Value 00hParallel/Serial Access Trap AMD Geode SC1200/SC1201 Processor Data Book 205 Primary Hard Disk Access Trap Floppy Disk Access TrapIndex 83h Power Management Enable Register 4 R/W 206 AMD Geode SC1200/SC1201 Processor Data Book 207 Index 84h Second Level PME/SMI Status Mirror Register 1 RO 208 AMD Geode SC1200/SC1201 Processor Data Book 209 Reserved. Always reads Index 88h General Purpose Timer 1 Count Register R/W210 Second Millisecond Re-trigger General Purpose Timer 1 on Floppy Disk ActivityAMD Geode SC1200/SC1201 Processor Data Book 211 Index 8Dh Video Speedup Timer Count Register R/W Index 8Bh General Purpose Timer 2 Control Register R/W212 Index 93h Index 8Fh-92hAMD Geode SC1200/SC1201 Processor Data Book 213 Index 97h Index 9Ah-9Bh Floppy Disk Idle Timer Count Register R/WIndex 98h-99h 214 Index A8h-A9h Video Overflow Count Register R/W Index A6h-A7h Video Idle Timer Count Register R/W Index AFh Suspend Notebook Command Register WO Index AEh CPU Suspend Command Register WOIndex B0h-B3h Index B4h Index BAh PIT Shadow Register RO Index B9h PIC Shadow Register ROAMD Geode SC1200/SC1201 Processor Data Book 217 Reserved. Set to CPU Clock Stop Index BCh Clock Stop Control Register R/W Reset Value 00hIndex BDh-BFh Index C0h-C3h Mask Bit Description Index CChIndex CDh Index CEh Index F4h Index EDh-F3hIndex F5h Second Level PME/SMI Status Register 2 RC 220 AMD Geode SC1200/SC1201 Processor Data Book 221 Index F6h Second Level PME/SMI Status Register 3 RC Reserved. Read as Index F7h Second Level PME/SMI Status Register 4 RC222 Index F8h-FFh I/O mapped registers accessed through F0BAR0 30. F0BAR0+I/O Offset Gpio Configuration RegistersGpio Support Registers Ration registers are located. -29gives the bit formats F0BAR0+I/O Offset 18h is set, this edge generates a PME Offset 14h-17h GPDI1 Gpio Data In 1 Register RO316 Reserved. Must be set to AMD Geode SC1200/SC1201 Processor Data Book 225 010010 = GPIO18 ball AG1 000011 Bank010011 = GPIO19 ball C9 000100 010100 = GPIO20 balls A9, N31 000101 AMD Geode SC1200/SC1201 Processor Data Book 227 LPC Support Registers 31. F0BAR1+I/O Offset LPC Interface Configuration Registers3121 Reserved. Set to AMD Geode SC1200/SC1201 Processor Data Book 229 230 Polarity selection Serial IRQ Interface Mode Reserved Serial IRQ EnableNumber of IRQ Data Frames AMD Geode SC1200/SC1201 Processor Data Book 231 232 LPC Game Port 0 Address Select. Selects I/O Port LPC Game Port 1 Address Select. Selects I/O PortLPC Floppy Disk Controller Address Select. Selects I/O Port LPC Midi Address Select. Selects I/O Port 234 Bit 32. F1 PCI Header Registers for SMI Status and Acpi Support SMI Status and Acpi Registers Function SMI Status Support Registers 33. F1BAR0+I/O Offset SMI Status RegistersCore Logic Module SMI Status and Acpi Registers Function AMD Geode SC1200/SC1201 Processor Data Book 237 Offset 02h-03h Top Level PME/SMI Status Register RO/RC Suspend Modulation Enable Mirror. Read to Clear238 AMD Geode SC1200/SC1201 Processor Data Book 239 Yes To enable SMI generation, set F0 Index 82h5 = Yes To enable SMI generation, set F0 Index 82h6 =Offset 04h-05h 240 AMD Geode SC1200/SC1201 Processor Data Book 241 These addresses should not be written Offset 1Ch-1Fh Offset 0Ah-1Bh242 3124 Offset 24h-27h External SMI Register R/WAMD Geode SC1200/SC1201 Processor Data Book 243 244 AMD Geode SC1200/SC1201 Processor Data Book 245 50h-FFh Offset 28h-4Fh Not Used Reset Value 00h246 34. F1BAR1+I/O Offset Acpi Support Registers Offset 06h Smicmd OS/BIOS Requests Register R/WAcpi Support Registers Clkval Clock Throttling Value. CPU duty cycle 248 SCI generation is always enabled 1511 Offset 0Ah-0Bh PM1AEN PM1A PME/SCI Enable Register R/WOffset 0Ch-0Dh PM1ACNT PM1A Control Register R/W 1514 Reserved. Must be set to 250 AMD Geode SC1200/SC1201 Processor Data Book 251 252 Gpwio Control Register 2 R/W Reset Value 00h Reserved Gpwio Control Register 1 R/W Reset Value 00hConsumer Electronic Infrared 02h0 Reserved Reset Value 00h 254 Gpwio Data Register R/W Reset Value 00h Bit Description Offset 18h-1Bh Reset Value 00000F00hOffset 21h-FFh AMD Geode SC1200/SC1201 Processor Data Book 255 IDE Controller Registers Function Core Logic Module IDE Controller Registers Function PIOMODE. PIO modeBit Description Index 30h-3Fh AMD Geode SC1200/SC1201 Processor Data Book 257 258 Index 50h-53h Bit Description Index 48h-4BhIndex 58h-5Bh Index 60h-FFh 260 IDE Controller Support Registers Offset 0Ah Offset 09hOffset 0Bh Offset 0Ch-0Fh Audio Registers Function 37. F3 PCI Header Registers for Audio Configuration Audio Support Registers 38. F3BAR0+Memory Offset Audio Configuration RegistersCore Logic Module Audio Registers Function Offset 04h-07h 264 AMD Geode SC1200/SC1201 Processor Data Book 265 2316 These bits change only on a fast write to an even address266 AMD Geode SC1200/SC1201 Processor Data Book 267 268 Mask Internal IRQ14. Write Only Mask Internal IRQ15. Write OnlyMask Internal IRQ11. Write Only Mask Internal IRQ10. Write Only Mask Internal IRQ3. Write Only Mask Internal IRQ4. Write OnlyAssert Masked Internal IRQ14 Reserved. Set to Assert Masked Internal IRQ12 AMD Geode SC1200/SC1201 Processor Data Book 271 Bit Description Assert Masked Internal IRQ1 Offset 29h Audio Bus Master 1 SMI Status Register RC Audio Bus Master 1 Command Register R/W Reset Value 00hOffset 2Ah-2Bh Offset 2Ch-2Fh Offset 31h Audio Bus Master 2 SMI Status Register RC Audio Bus Master 2 Command Register R/W Reset Value 00hOffset 32h-33h Offset 34h-37h Offset 39h Audio Bus Master 3 SMI Status Register RC Audio Bus Master 3 Command Register R/W Reset Value 00hOffset 3Ah-3Bh Offset 3Ch-3Fh Offset 41h Audio Bus Master 4 SMI Status Register RC Audio Bus Master 4 Command Register R/W Reset Value 00hOffset 42h-43h Offset 44h-47h Offset 49h Audio Bus Master 5 SMI Status Register RC Audio Bus Master 5 Command Register R/W Reset Value 00hOffset 4Ah-4Bh Offset 4Ch-4Fh 39. F5 PCI Header Registers for X-Bus Expansion Bus Expansion Interface Function Index 20h-23h Bit Description Index 1Ch-1FhIndex 24h-27h Index 28h-2Bh Index 48h-4Bh F5BAR2 Mask Address Register R/W Index 58h F5BARx Initialized Register R/W Reset Value 00hIndex 4Ch-4Fh F5BAR3 Mask Address Register R/W Index 50h-53h F5BAR4 Mask Address Register R/W Index 68h-FFh Bit Description Index 64h-67h280 Bus Expansion Support Registers 40. F5BAR0+I/O Offset X-Bus Expansion RegistersF5 Index 10h, Base Address Register 0 F5BAR0 set USB transceivers. Default = Three USB transceivers. Default = 128Iotestporten Debug Test Port Enable 282 USB Controller Registers Pciusb 41. Pciusb USB PCI Configuration RegistersCore Logic Module USB Controller Registers Pciusb AMD Geode SC1200/SC1201 Processor Data Book 283 Index 0Dh Latency Timer Register R/W Reset Value 08hBit Description Index 06h-07h Status Register R/W Reserved. Must be set to Index 08h 42. USBBAR+Memory Offset USB Controller Registers 286 32579BCore Logic Module USB Controller Registers Pciusb OwnershipChangeEnable HcInterruptEnable Register R/W Reset Value = 00000000hRootHubStatusChangeEnable FrameNumberOverflowEnable Offset 20h-23h Bit Description StartOfFrameEnableOffset 24h-27h Offset 28h-2Bh Reset Value = 01000003h Reset Value = 00000628hBit Description Offset 38h-3Bh HcFrameRemaining Register RO Reserved. Read 0s Read LocalPowerStatusChange. Not supported. Always read BalPowerOffset 50h-53h HcRhStatus Register R/W 3018 Read PortResetStatus HcRhPortStatus1 Register R/W Reset Value = 00000000hRead PortSuspendStatus AMD Geode SC1200/SC1201 Processor Data Book 291 Read CurrentConnectStatus Read PortEnableStatus292 AMD Geode SC1200/SC1201 Processor Data Book 293 Reserved Reset Value = xxh 294 AMD Geode SC1200/SC1201 Processor Data Book 295 43. DMA Channel Control Registers ISA Legacy Register Space Timing Mode Priority ModeCore Logic Module ISA Legacy Register Space Write Channel Number Mode Select Transfer Mode32579BCore Logic Module ISA Legacy Register Space Bit Description Port 00Bh Undefined Write DMA Command Register, ChannelsAMD Geode SC1200/SC1201 Processor Data Book 299 Port 0D4h Bit Description Port 0D2hPort 0D6h Port 0D8h 44. DMA Page Registers 45. Programmable Interval Timer Registers Bit Description Port 042h Write Current Counter Mode BCD ModeCounter Value Read Port 043h R/W 46. Programmable Interrupt Controller Registers Register Read Mode Poll CommandBit Description IRQ1 / IRQ9 Mask IRQ0 / IRQ8 Mask IRQ6 / IRQ14 In-Service Interrupt Service Register IRQ7 / IRQ15 In-ServiceIRQ5 / IRQ13 In-Service IRQ4 / IRQ12 In-Service 47. Keyboard Controller Registers 49. Miscellaneous Registers 48. Real-Time Clock Registers AMD Geode SC1200/SC1201 Processor Data Book 309 310 Video Input Port VIP Interface General FeaturesHardware Video Acceleration Graphics-Video Overlay and Blending Video Input Port Display ModesVIP Tvout Video Support Functional DescriptionVBI Support Video Processor Module Active Video Video Input Port VIP Direct Mode and Capture Mode Configurations Address not changed during runtime BobAMD Geode SC1200/SC1201 Processor Data Book 317 Weave Ping-pongs between the two buffers during runtime Capture VBI ModeAMD Geode SC1200/SC1201 Processor Data Book 319 Video Input Formatter Video BlockLine Buffer 320 Filtering Horizontal Downscaler with 4-Tap FilteringHorizontal Downscaler Maintaining Aspect Ratio Formatter Line Buffers2.5 2-Tap Vertical and Horizontal Upscalers Ai,j Ai,j+1 Ai+1,jAi+1,j+1 CSC Mixer/Blender BlockRGB RAM Filter2 Bit Mode Comment Valid Mixing/Blending ConfigurationsFlicker 324 Gamma Correction YUV to RGB CSC in Video Data PathRGB to YUV CSC 3.4 1/2 Y Flicker Filter Video Window Graphics WindowCursor Window Alpha Windows Mixing/Blending Operation Truth Table for Alpha BlendingColor CHROMASEL1 328 Tvout Block Flicker Filter, Interlaced Video YUV Mixing/Blending ModeFlicker Filter and Scan Rate Conversion Vesa Integrated DACs Vesa DDSC2B and Dpms Support TFT Interface Power SequenceHSYNC, VSYNC, TFTDE, Tftdck T1 is a programmable multiple of frame time T0+T1 Integrated PLL Divider Phase Charge LoopCompare Pump Filter Divider Out 332 F4 PCI Header Registers for Video Processor Support Summary F4BAR0 Video Processor Configuration Registers SummaryF4BAR0+ 334 32579BVideo Processor Module Register Summary F4BAR2 VIP Support Registers Summary Name Value Tvout Configuration RegistersEncoder Registers F4BAR2+ Reset Value 030000h Reset Value 0504hVideo Processor Registers Function 3112 VIP Base Address 110 Address Range. Read Only Index 3Eh-FFh Reserved Video Processor Module Video Processor Registers FunctionAMD Geode SC1200/SC1201 Processor Data Book 337 EN42X Enable 42x Format. Allows format selection Video Configuration Register R/W Reset Value 00000000hVideo Processor Support Registers F4BAR0 To 0 or 1 should be written with a value that is read Tions of the power sequence control lines 1614 Offset 04h-07h Display Configuration Register R/W3028 Ddcsdaout DDC Output Data. DDC data bit for output 340 Offset 08h-0Bh Video X Position Register R/W AMD Geode SC1200/SC1201 Processor Data Book 341 Bit Description 100 12 PLL2PWREN PLL2 Power-Down Enable Reset Value 00001400hBit Description Offset 1Ch-1Fh Block Offset 20h-23h Offset 40h-43h Video Downscaler Coefficient Register R/W DTS Downscale Type SelectFLTCO4 Filter Coefficient 4. For the tap-4 filter FLTCO3 Filter Coefficient 3. For the tap-3 filter Reset Value 0000xxxxh Reserved Signen Signature EnableReset Value 00060000h Bit Description Offset 44h-47h CRC Signature Register R/W AMD Geode SC1200/SC1201 Processor Data Book 345 100 i.e., shift one line otherwise, leave at Offset 54h-57h Bit Description Offset 50h-53hOffset 60h-63h Alpha Window 1 X Position Register R/W 346 Decremented until it is reloaded via bit 17 Loadalpha 3118AMD Geode SC1200/SC1201 Processor Data Book 347 348 Offset 94h-97h Offset 90h-93hOffset 400h-403h Video Fifo Underflow Empty VBI Fifo Underflow Empty Video Fifo OverFlow FullVBI Fifo Overflow Full Upscale horizontally VBI data by Bit Description Offset 414h-417h Genlocktouten GenLock Timeout Enable3120 Reserved 190 Port Offset 41Ch-41Fh Sggenlocken Enable a Single GenLock Function Ctgenlocken Enable Continuous GenLock FunctionOffset 424h-427h 3121 Reserved 200 Offset 810h-813h Bit Description Offset 80Ch-80Fh Fieldinvr Field Invert Horintp Horizontal InterpolationOffset 81Ch-81Fh Offset C00h-C03h AMD Geode SC1200/SC1201 Processor Data Book 355 2920 A23 Mode TV DAC Mode Bits Ball NoOffset C08h-C0Bh D24 A24 3114 Offset C24h-C27hOffset C28h-C2Bh AMD Geode SC1200/SC1201 Processor Data Book 357 Reset Value 00000004h Reset Value 00000020hBit Description Offset C2Ch-C2Fh Offset C50h-C53h VIP Support Registers F4BAR2 10. F4BAR2+Memory Offset VIP Configuration RegistersAll other decodes Reserved AMD Geode SC1200/SC1201 Processor Data Book 359 Capture Store to Memory Video Data Capture Store to Memory VBI DataReserved.Read Only Current Field. Read Only 2322 Reserved. Read Only Run Status. Read Only Video Data Capture Active. Read OnlyOffset 14h-17h Offset 24h-27h Video Data Even Base Register R/W Offset 2Ch-3Fh 3116 Reserved 150Offset 44h-47h VBI Data Even Base Register R/W Offset 48h-4Bh VBI Data Pitch Register R/W Testability Jtag Jtag Mode Instruction SupportMandatory Instruction Support Optional Instruction Support 364 Power/Ground Connections and Decoupling General SpecificationsElectro Static Discharge ESD Absolute Maximum Ratings Operating Conditions Symbol Parameter Min Typ Max Unit Comments366 Power Plane Signal Names VCC Balls VSS Balls Power Planes of External Interface SignalsPower State Parameter Definitions DC Current DC Characteristics for On State Symbol Parameter Note Min Typ Max Unit Comments DC Characteristics for Active Idle, Sleep, and Off StatesSymbol Parameter Min Typ Max Unit Comment Ball Capacitance and Inductance Balls with PU/PD Resistors Pull-Up and Pull-Down ResistorsVIO External PU or PD resistor Symbol Description Reference DC CharacteristicsWire 10. Buffer Types Inbtn DC Characteristics Inab DC CharacteristicsInpci DC Characteristics INT DC Characteristics Instrp DC CharacteristicsInts DC Characteristics INTS1 DC Characteristics ODn DC Characteristics Inusb DC Characteristics Op/n DC Characteristics Odpci DC CharacteristicsOpci DC Characteristics Ousb DC Characteristics 11. Default Levels for Measurement Switching Parameters AC CharacteristicsSymbol Parameter Value CLK Outputs Memory Controller InterfaceInputs 12. Memory Controller Timing Parameters 32579BElectrical SpecificationsSDCLK30, Sdclkout high time 13.5 SDCLK30 Control Output, MA120 T1, t2, t3 t10BA10, MD630 MD630 Data Valid Read Data Vpckin Vref 14. Video Output Port Timing Parameters 15. TFT Timing Parameters CRT and TFT Interface 16. CRT Vesa Compatible DAC RED, GREEN, and Blue Outputs Symbol Parameter Note Min Max Unit Comments IRE RESLSB DNL LSB Tvref 18. ACCESS.bus Input Timing Parameters ACCESS.bus Interface19. ACCESS.bus Output Timing Parameters AB1C AB2C AB1D AB2D AB1D AB2D AB1C AB1D AB2D AB1C AB2CAMD Geode SC1200/SC1201 Processor Data Book 387 PCI Bus 20. PCI AC Specifications Equation a Equation B 64VIO Pciclk 0.4 V IO 21. PCI Clock Parameters 22. PCI Timing Parameters 23. Measurement Condition Parameters Symbol Value Unit CommentsMeasurement and Test Conditions Signals PowerInput Valid Ms typ Sub-ISA Interface Symbol Parameter Bits Type Comments24. Sub-ISA Timing Parameters Bus Width Min MEMR#/DOCR#/IOR# Bus Width Min Max Symbol Parameter Bits Type Comments IOR#/RD#/TRDE# ROMCS#/DOCCS#MEMR#/DOCR# IOW#/WR# MEMW#/DOCW# IOCS10# DOCCS#/ROMCS#IOW#/WR# MEMW#/DOCW# TRDE# D150 LPC Interface 25. LPC and Serirq IDE signals rise time from 0.1V IO to 0.9V IO = 40 pF IDE signals fall time from 0.9V IO to 0.1V IO = 40 pFIDE Interface Timing 26. IDE General Timing Parameters IDERST# pulse width 27. IDE Register Transfer to/from Device Timing Parameters Mode Symbol Parameter Unit CommentsCycle time min Width 8-bit min IDEIOR0# IDEIOW0# Write IDEDATA70 Addr valid1Read IDEDATA70 IDEIORDY0 2,3 165 125 100 28. IDE PIO Data Transfer to/from Device Timing Parameters402 Read IDEDATA150 IDEIOR0# IDEIOW0# Write IDEDATA150AMD Geode SC1200/SC1201 Processor Data Book 403 29. IDE Multiword DMA Data Transfer Timing Parameters IDEDREQ0 IDEDACK0# IDEIOR0# IDEIOW0# IDECS10#AMD Geode SC1200/SC1201 Processor Data Book 405 30. IDE UltraDMA Data Burst Timing Parameters Mode Symbol Parameter Min Max Unit Comments406 STOP0 IDEREQ0IDEIOR0# HDMARDY0# IDEIRDY0 DSTROBE0 IDEDATA150 at device IDEIRDY0 DSTROBE0 at host IDEIRDY0 DSTROBE0 at deviceIDEDATA150 at host 408 IDEIOW0#STOP0# host IDEDREQ0 device IDEDACK0# hostIDEIOR0#HDMARDY0# AMD Geode SC1200/SC1201 Processor Data Book 409 IDEIOW0# STOP0# IDEDREQ0 device410 IDEIRDY0 DSTROBE0 device IDEDATA150 device IDEIOW0# STOP0# host IDEIOR0# HDMARDY0# hostIDECS01# IDEADDR20 IDEIOW0# STOP0# host DevicetUI IDEDACK0# hostIDEIORDY0 DDMARDY0 device IDEIOR0# HSTROBE0# host At host HSTROBE0#IDEDATA150 At host IDEIOR0# HSTROBE0# at device IDEDATA150 at device IDEIORDY0# DDMARDY0# IDEDREQ0 device IDEDACK0# host IDEIOW0# STOP0# hostIDEIOR0# HSTROBE0# 414 IDEDATA150 host IDEADDR20 IDECS01# IDEIORDY0# DDMARDY0# deviceIDEDACK0# host AMD Geode SC1200/SC1201 Processor Data Book 415 IDEDATA150 host IDECS01# IDEADDR20 IDEDREQ0 device IDEDACK0 host IDEIOW0# STOP0# host416 Full Speed Receiver EOP Width Note Universal Serial Bus USB 31. USB Timing ParametersLow Speed Source Note Host upstream Source EOP widthReceiver data jitter tolerance for paired Low Speed Receiver EOP Width Note Differential Data Lines Rise Time Fall TimeDifferential Data Lines Crossover Points 2.0 Consecutive Transitions Data Crossover Level Differential Data to SE0 SkewEOP Width Differential Crossover Points Data Lines TCPN + Transmitter Sharp-IR and Consumer Remote Control Modulation signal periodSIR signal pulse width Setting of the Rxhsc bit bit 5 of the Rccfg register MIR Fast IR Port Timing 33. Fast IR Port Timing ParametersFIR STB# Busy ACK# 35. Enhanced Parallel Port Timing Parameters Symbol Parameter MinUnit Comments Extended Capabilities Port ECP Timing 36. ECP Forward Mode Timing ParametersAFD# Busy BUSY# 37. ECP Reverse Mode Timing Parameters AC97RST# inactive to Bitclk 162.8 Startup delay Audio Interface Timing AC97 38. AC Reset Timing ParametersSync inactive to Bitclk startup 162.8 Delay AC97RST# active low pulse width AC97CLK Vold 40. AC97 Clocks Parameters SDATAOUT/SYNC SDATAIN, SDATAIN2 41. AC97 I/O Timing Parameters 42. AC97 Signal Rise and Fall Timing Parameters End of Slot 2 to Bitclk Sdatain low 43. AC97 Low Power Mode Timing ParametersSlot Bitclk Sdataout Power management event to ONCTL# Assertion Power Management44. PWRBTN# Timing Parameters ONCTL# PWRBTN# PWRBTN# ONTCL# PWRCNT21 POR# 434 POR# 32KHZ Non-test inputs setup time TDI, TMS setup timeJtag Interface 48. Jtag Timing Parameters TDI, TMS hold time Input Signals Output SignalsTDI TMS TDO 436 ΘJC ×C/W Thermal CharacteristicsCase-to-Ambient Thermal Resistance Example @ 85C Example Heatsink ConsiderationsAssume P max = 5W and TA max = 40C Therefore Assume P max = 9W and TA max = 40C Therefore Package Specifications Physical DimensionsAMD Geode SC1200/SC1201 Processor Data Book 439 440 BGU481 Package Bottom View Macrovision Product Notice Order InformationOrdering Part Number Core Frequency MHz Table A-1. Revision History Data Book Revision HistoryRevision # Revisions / Comments