AMD SC1201, SC1200 manual ACCESS.bus Interface Signals, PCI Bus Interface Signals

Signal Definitions 32579B

3.4.6ACCESS.bus Interface Signals

Signal Name	Ball No.	Type	Description	Mux
AB1C	N31	I/O	ACCESS.bus 1 Serial Clock. This is the serial clock for	GPIO20+DOCCS#
			the interface.
			Note: If selected as AB1C function but not used, tie
			AB1C high.
AB1D	N30	I/O	ACCESS.bus 1 Serial Data. This is the bidirectional	GPIO1+IOCS1#
			serial data signal for the interface.
			Note: If AB1D function is selected but not used, tie
			AB1D high.
AB2C	N29	I/O	ACCESS.bus 2 Serial Clock. This is the serial clock for	GPIO12
			the interface.
			Note: If AB2C function is selected but not used, tie
			AB2C high.
AB2D	M29	I/O	ACCESS.bus 2 Serial Data. This is the bidirectional	GPIO13
			serial data signal for the interface.
			Note: If AB2D function is selected but not used, tie
			AB2D high.

3.4.7PCI Bus Interface Signals

Signal Name	BalL No.	Type	Description	Mux
PCICLK	A7	I	PCI Clock. PCICLK provides timing for all transactions	---
			on the PCI bus. All other PCI signals are sampled on the
			rising edge of PCICLK, and all timing parameters are
			defined with respect to this edge.
PCICLK0	A4	O	PCI Clock Outputs. PCICLK0 and PCICLK1 provide	FPCI_MON (Strap)
			clock drives for the system at 33 MHz. These clocks are
PCICLK1	D6	O		LPC_ROM (Strap)
			asynchronous to PCI signals. There is low skew between
			all outputs. One of these clock signals should be con-
			nected to the PCICLK input. All PCI clock users in the
			system (including PCICLK) should receive the clock with
			as low a skew as possible.
AD[31:24]	See	I/O	Multiplexed Address and Data. A bus transaction con-	D[7:0]
	Table 3-3		sists of an address phase in the cycle in which FRAME#
AD[23:0]				A[23:0]
	on page		is asserted followed by one or more data phases. During
	40		the address phase, AD[31:0] contain a physical 32-bit
			address. For I/O, this is a byte address. For configuration
			and memory, it is a DWORD address. During data
			phases, AD[7:0] contain the least significant byte (LSB)
			and AD[31:24] contain the most significant byte (MSB).
C/BE3#	H4	I/O	Multiplexed Command and Byte Enables. During the	D11
			address phase of a transaction when FRAME# is active,
C/BE2#	F3			D10
			C/BE[3:0]# define the bus command. During the data
C/BE1#	J2			D9
			phase, C/BE[3:0]# are used as byte enables. The byte
			enables are valid for the entire data phase and determine
C/BE0#	L1			D8
			which byte lanes carry meaningful data. C/BE0# applies
			to byte 0 (LSB) and C/BE3# applies to byte 3 (MSB).

AMD Geode™ SC1200/SC1201 Processor Data Book 55