Video Processor Module - Register Summary

32579B

Table 7-6. F4BAR0: Video Processor Configuration Registers Summary (Continued)

F4BAR0+

 

 

 

 

 

Memory

Width

 

 

Reset

Reference

Offset

(Bits)

Type

Name

Value

(Table 7-9)

 

 

 

 

 

 

TVOUT Configuration Registers

 

 

 

 

 

 

 

 

 

800h-803h

32

R/W

Horizontal Timing Register

00000000h

Page 352

 

 

 

 

 

 

804h-807h

32

R/W

Horizontal Sync Timing Register

00000000h

Page 352

 

 

 

 

 

 

808h-80Bh

32

R/W

Vertical Sync Timing Register

00000000h

Page 352

 

 

 

 

 

 

80Ch-80Fh

32

R/W

Display Line End Register

00000000h

Page 353

 

 

 

 

 

 

810h-813h

32

R/W

Horizontal Pre Encoder Scale Register

00000000h

Page 353

 

 

 

 

 

 

814h-817h

32

R/W

Horizontal Scaling Control Register

00000000h

Page 353

 

 

 

 

 

 

818h-81Bh

32

R/W

TVOUT Debug Register

00000440h

Page 354

 

 

 

 

 

 

81Ch-81Fh

32

---

Reserved

---

Page 354

 

 

 

 

 

 

Encoder Registers

 

 

 

 

 

 

 

 

 

 

C00h-C03h

32

R/W

Timing and Encoder Control 1 Register

00000000h

Page 354

 

 

 

 

 

 

C04h-C07h

32

R/W

Timing and Encoder Control 2 Register

1FF00000h

Page 355

 

 

 

 

 

 

C08h-C0Bh

32

R/W

Timing and Encoder Control 3 Register

00000000h

Page 356

 

 

 

 

 

 

C0Ch-C0Fh

32

R/W

Subcarrier Frequency Register

21F07C1Fh

Page 356

 

 

 

 

 

 

C10h-C13h

32

R/W

Display Position Register

00120071h

Page 356

 

 

 

 

 

 

C14h-C17h

32

R/W

Display Size Register

00EF02CFh

Page 356

 

 

 

 

 

 

C18h-C1Bh

32

R/W

Closed Captioning Data Register

00000000h

Page 357

 

 

 

 

 

 

C1Ch-C1Fh

32

R/W

Extended Data Services Data Register

00000000h

Page 357

 

 

 

 

 

 

C20h-C23h

32

R/W

CGMS Data Register

00000000h

Page 357

 

 

 

 

 

 

C24h-C27h

32

R/W

WSS Data Register

00000000h

Page 357

 

 

 

 

 

 

C28h-C2Bh

32

R/W

Closed Captioning Control Register

00000000h

Page 357

 

 

 

 

 

 

C2Ch-C2Fh

32

R/W

DAC Control Register

00000020h

Page 358

 

 

 

 

 

 

C50h-C53h

32

R/W

VBI Scaler Register

00000004h

Page 358

 

 

 

 

 

 

Table 7-7. F4BAR2: VIP Support Registers Summary

F4BAR2+

 

 

 

 

 

Memory

Width

 

 

Reset

Reference

Offset

(Bits)

Type

Name

Value

(Table 7-10)

 

 

 

 

 

 

00h-03h

32

R/W

Video Interface Port Configuration Register

00000000h

Page 359

 

 

 

 

 

 

04h-07h

32

R/W

Video Interface Control Register

00000000h

Page 359

 

 

 

 

 

 

08h-0Bh

32

R/W

Video Interface Status Register

xxxxxxxxh

Page 360

 

 

 

 

 

 

0Ch-0Fh

--

--

Reserved

00000000h

Page 361

 

 

 

 

 

 

10h-13h

32

RO

Video Current Line Register

xxxxxxxxh

Page 361

 

 

 

 

 

 

14h-17h

32

R/W

Video Line Target Register

00000000h

Page 361

 

 

 

 

 

 

18h-1Bh

32

R/W

Odd Field VBI Line Enable Register

00000000h

Page 361

 

 

 

 

 

 

1Ch-1Fh

32

R/W

Even Field VBI Line Enable Register

00000000h

Page 361

 

 

 

 

 

 

20h-23h

32

R/W

Video Data Odd Base Register

00000000h

Page 361

 

 

 

 

 

 

24h-27h

32

R/W

Video Data Even Base Register

00000000h

Page 361

 

 

 

 

 

 

28h-2Bh

32

R/W

Video Data Pitch Register

00000000h

Page 362

 

 

 

 

 

 

2Ch-3Fh

--

--

Reserved

00000000h

Page 362

 

 

 

 

 

 

40h-43h

32

R/W

VBI Data Odd Base Register

00000000h

Page 362

 

 

 

 

 

 

44h-47h

32

R/W

VBI Data Even Base Register

00000000h

Page 362

 

 

 

 

 

 

48h-4Bh

32

R/W

VBI Data Pitch Register

00000000h

Page 362

 

 

 

 

 

 

4Ch-1FFh

--

--

Reserved

00000000h

Page 362

 

 

 

 

 

 

 

 

 

 

 

 

AMD Geode™ SC1200/SC1201 Processor Data Book

 

335

Page 335
Image 335
AMD SC1201 F4BAR2 VIP Support Registers Summary, Name Value Tvout Configuration Registers, Encoder Registers, F4BAR2+