AMD SC1200, SC1201 manual IDE Multiword DMA Data Transfer Timing Parameters

32579BElectrical Specifications

Table 9-29. IDE Multiword DMA Data Transfer Timing Parameters

			Mode
Symbol	Parameter	0	1	2	Unit	Comments
t0	Cycle time (min)	480	150	120	ns	Note 1
tD	IDE_IOR[0:1]#/IDE_IOW[0:1]# (min)	215	80	70	ns
tE	IDE_IOR[0:1]# data access (max)	150	60	50	ns
tF	IDE_IOR[0:1]# data hold (min)	5	5	5	ns
tG	IDE_IOW[0:1]#/IDE_IOW[0:1]# data setup	100	30	20	ns
	(min)
tH	IDE_IOW[0:1]# data hold (min)	20	15	10	ns
tI	IDE_DACK[0:1]# to	0	0	0	ns
	IDE_IOR[0:1]#/IDE_IOW[0:1]# setup
	(min)
tJ	IDE_IOR[0:1]#/IDE_IOW[0:1]# to	20	5	5	ns
	IDE_DACK[0:1]# hold (min)
tKR	IDE_IOR[0:1]# negated pulse width (min)	50	50	25	ns
tKW	IDE_IOW[0:1]# negated pulse width (min)	215	50	25	ns
tLR	IDE_IOR[0:1]# to IDE_DREQ[0:1] delay	120	40	35	ns
	(max)
tLW	IDE_IOW[0:1]# to IDE_DREQ0,1 delay	40	40	35	ns
	(max)
tM	IDE_CS[0:1]# valid to	50	30	25	ns
	IDE_IOR[0:1]#/IDE_IOW[0:1]# (min)
tN	IDE_CS[0:1]# hold	15	10	10	ns
tZ	IDE_DACK[0:1]# to TRI-STATE	20	25	25	ns

Note 1. t0 is the minimum total cycle time, tD is the minimum command active time, and tKR or tKW is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the command active time and the

command inactive time. The three timing requirements of t0, tD and tKR/KW, are met. The minimum total cycle time requirement t0 is greater than the sum of tD and tKR/KW. (This means that a host implementation can lengthen tD and/or tKR/KW to ensure that t0 is equal to or greater than the value reported in the device’s IDENTIFY DEVICE data.)

404 AMD Geode™ SC1200/SC1201 Processor Data Book