AMD SC1200, SC1201 Banks 0 and 1 Common Control and Status Registers 118, 119, 166, 167, 180, 182

	32579B	List of Tables
Table 5-29.	Banks 0 and 1 - Common Control and Status Registers	. . . . . . 118
Table 5-30.	Bank 1 - CEIR Wakeup Configuration and Control Registers	. . . . . . 119
Table 5-31.	ACB Register Map	. . . . . . 126
Table 5-32.	ACB Registers	. . . . . . 126
Table 5-33.	Parallel Port Register Map for First Level Offset	. . . . . . 129
Table 5-34.	Parallel Port Register Map for Second Level Offset	. . . . . . 129
Table 5-35.	Parallel Port Bit Map for First Level Offset	. . . . . . 130
Table 5-36.	Parallel Port Bit Map for Second Level Offset	. . . . . . 130
Table 5-37.	Bank 0 Register Map	. . . . . . 131
Table 5-38.	Bank Selection Encoding	. . . . . . 132
Table 5-39.	Bank 1 Register Map	. . . . . . 132
Table 5-40.	Bank 2 Register Map	. . . . . . 132
Table 5-41.	Bank 3 Register Map	. . . . . . 132
Table 5-42.	Bank 0 Bit Map	. . . . . . 133
Table 5-43.	Bank 1 Bit Map	. . . . . . 133
Table 5-44.	Bank 2 Bit Map	. . . . . . 134
Table 5-45.	Bank 3 Bit Map	. . . . . . 134
Table 5-46.	Bank 0 Register Map	. . . . . . 135
Table 5-47.	Bank Selection Encoding	. . . . . . 136
Table 5-48.	Bank 1 Register Map	. . . . . . 136
Table 5-49.	Bank 2 Register Map	. . . . . . 136
Table 5-50.	Bank 3 Register Map	. . . . . . 137
Table 5-51.	Bank 4 Register Map	. . . . . . 137
Table 5-52.	Bank 5 Register Map	. . . . . . 137
Table 5-53.	Bank 6 Register Map	. . . . . . 138
Table 5-54.	Bank 7 Register Map	. . . . . . 138
Table 5-55.	Bank 0 Bit Map	. . . . . . 138
Table 5-56.	Bank 1 Bit Map	. . . . . . 139
Table 5-57.	Bank 2 Bit Map	. . . . . . 139
Table 5-58.	Bank 3 Bit Map	. . . . . . 139
Table 5-59.	Bank 4 Bit Map	. . . . . . 139
Table 5-60.	Bank 5 Bit Map	. . . . . . 140
Table 5-61.	Bank 6 Bit Map	. . . . . . 140
Table 5-62.	Bank 7 Bit Map	. . . . . . 140
Table 6-1.	Physical Region Descriptor Format	. . . . . . 145
Table 6-2.	UltraDMA/33 Signal Definitions	. . . . . . 146
Table 6-3.	Cycle Multiplexed PCI / Sub-ISA Balls	. . . . . . 151
Table 6-4.	PIC Interrupt Mapping	. . . . . . 155
Table 6-5.	Wakeup Events Capability	. . . . . . 159
Table 6-6.	Power Planes Control Signals vs. Sleep States	. . . . . . 160
Table 6-7.	Power Planes vs. Sleep/Global States	. . . . . . 160
Table 6-8.	Power Management Events	. . . . . . 160
Table 6-9.	Device Power Management Programming Summary	. . . . . . 166
Table 6-10.	Bus Masters That Drive Specific Slots of the AC97 Interface	. . . . . . 167
Table 6-11.	Physical Region Descriptor Format	. . . . . . 168
Table 6-12.	Cycle Types	. . . . . . 174
Table 6-13.	PCI Configuration Address Register (0CF8h)	. . . . . . 175
Table 6-14.	F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support Summary . . . 176
Table 6-15.	F0BAR0: GPIO Support Registers Summary	. . . . . . 179
Table 6-16.	F0BAR1: LPC Support Registers Summary	. . . . . . 179
Table 6-17.	F1: PCI Header Registers for SMI Status and ACPI Support Summary	. . . . . . 180
Table 6-18.	F1BAR0: SMI Status Registers Summary	. . . . . . 180
Table 6-19.	F1BAR1: ACPI Support Registers Summary	. . . . . . 181
Table 6-20.	F2: PCI Header Registers for IDE Controller Support Summary	. . . . . . 182
Table 6-21.	F2BAR4: IDE Controller Support Registers Summary	. . . . . . 183
10	AMD Geode™ SC1200/SC1201 Processor Data Book