AMD SC1201, SC1200 manual Universal Serial Bus, Sub-ISA Bus Interface, IOCS0#/IOCS1#, Docw

Core Logic Module 32579B

6.2.4Universal Serial Bus

The Core Logic module provides three complete, indepen- dent USB ports. Each port has a Data “Negative” and a Data “Positive” signal.

The USB ports are Open Host Controller Interface (Open- HCI) compliant. The OpenHCI specification provides a reg- ister-level description for a host controller, as well as common industry hardware/software interface and drivers.

6.2.5Sub-ISA Bus Interface

The Sub-ISA interface of the Core Logic module is an ISA- like bus interface that is used by SC1200/SC1201 proces- sor to interface with Boot Flash, M-Systems DiskOnChip or NAND EEPROM and other I/O devices. The Core Logic module is the default subtractive decoding agent and for- wards all unclaimed memory and I/O cycles to the ISA bus. However, the Core Logic module can be configured to ignore either I/O, memory, or all unclaimed cycles (subtrac- tive decode disabled).

Note: The external Sub-ISA bus is a positive decode bus. Unclaimed memory and I/O cycles will not appear on the Sub-ISA interface.

The Core Logic module does not support Sub-ISA refresh cycles. The refresh toggle bit in Port B still exists for soft- ware compatibility reasons.

The Sub-ISA interface includes the followings signals in addition to the signals used for an ISA interface:

•IOCS0#/IOCS1#

—Asserted on I/O read/write transactions from/to a programmable address range.

•DOCCS#

—Asserted on memory read/write transactions from/to a programmable window.

•ROMCS#

—Asserted on memory read/write to upper 16 MB of address space. Configurable via the ROM Mask register (F0 Index 6Ch).

•DOCR#

—DOCR# is asserted on memory read transactions from DOCCS# window (i.e., when both DOCCS# and MEMR# are active, DOCR# is active; otherwise, it is inactive).

•DOCW

—DOCW# is asserted on memory write transactions to DOCCS# window (i.e., when both DOCCS# and MEMW# are active, DOCW# is active; otherwise, it is inactive).

•RD#, WR#

—The signals IOR#, IOW#, MEMR#, and MEMW# are combined into two signals: RD# is asserted on I/O read or memory read; WR# is asserted on I/O write or memory write.

Memory devices that use ROMCS# or DOCCS# as their chip select signal can be configured to support an 8-bit or 16-bit data bus via bits 3 and 6 of the MCR register. Such devices can also be configured as zero wait states devices (regardless of the data bus width) via bits 9 and 10 of the MCR register. For MCR register bit descriptions, see Table 4-2 on page 72.

I/O peripherals that use IOCS0# or IOCS1# as their chip select signal can be configured to support an 8-bit or 16-bit data bus via bits 7 and 8 of the MCR register. Such devices can also be configured as zero wait state devices (for 8-bit peripherals) via bits 11 and 12 of the MCR register. For MCR register bit descriptions, see Table 4-2 on page 72.

Other memory devices and I/O peripherals must be 8-bit devices; their transactions can not be with zero wait states

The Boot Flash supported by the SC1200/SC1201 proces- sor can be up to 16 MB. It is supported with the ROMCS# signal.

All unclaimed memory and I/O cycles are forwarded to the Internal ISA bus if subtractive decode is enabled.

The DiskOnChip chip select signal (DOCCS#) is asserted on any memory read or memory write transaction from/to a programmable address range. The address range is pro- grammable via the DOCCS# Base Address and Control registers (F0 Index 78h and 7Ch). The base address must be on an address boundary, the size of the range.

Signal DOCCS# can also be used to interface to NAND Flash devices together with signals DOCW# and DOCR#. See application note AMD Geode™ SC1200/SC2200/ SC3200 Processors: External NAND Flash Memory Circuit for details.

AMD Geode™ SC1200/SC1201 Processor Data Book 147