AMD SC1200 Power Planes Control Signals vs Sleep States, Power Planes vs. Sleep/Global States

32579B Core Logic Module

6.2.9.3Power Planes Control

The SC1200/SC1201 processor supports up to three power planes. Three signals are used to control these power planes. Table 6-6describes the signals and when each is asserted.

Table 6-6. Power Planes Control Signals vs.

Sleep States

					SL4
					and
Signal	S0	SL1	SL2	SL3	SL5
PWRCNT1	1	1	0	0	0
PWRCNT2	1	1	1	0	0
ONCTL#	0	0	0	0	1

These signals allow control of the power of system devices and the SC1200/SC1201 processor itself. Table 6-7describes the SC1200/SC1201 processor’s power planes with respect to the different Sleep and Global states.

Table 6-7. Power Planes vs. Sleep/Global States

	VCORE,
Sleep/	VCCCRT, VI/O,
Global	AVCCTV, VPLL,	VSB, VSBL	VBAT
State	AVCCCRT
S0, SL1 and	On	On	On or Off
SL2
SL3, SL4	Off	On	On or Off
and SL5
G3	Off	Off	On
No Power	Off	Off	Off
Illegal	On	Off	On or Off

The SC1200/SC1201 processor’s power planes are con- trolled externally by the three signals (i.e., the system designer should make sure the system design is such that Table 6-7is met) for all supported Sleep states.

VSB and VBAT are not controlled by any control signal. VSB exists as long as the AC power is plugged in (for desktop

systems) or the main battery is charged (for mobile sys- tems). VBAT exists as long as the RTC battery is charged.

The case in which VSB does not exist is called Mechanical Off (G3).

6.2.9.4Power Management Events

The SC1200/SC1201 processor supports power manage- ment events that can manage:

•Transition of the system from a Sleep state to a Work state. This is done by the hardware. These events are defined as wakeup events.

•Enabled wakeup events to set the WAK_STS bit (F1BAR1+I/O Offset 08h[15]) to 1, when transitioning the system back to the working state.

•Generation of an interrupt. This invokes the relevant software driver. The interrupt can either be an SMI or SCI (selected by the SCI_EN bit, F1BAR1+I/O Offset 0Ch[0]). These events are defined as interrupt events.

Table 6-8lists the power management events that can gen- erate an SCI or SMI.

Table 6-8. Power Management Events

Event	SCI	SMI
Power Button	Yes	Yes
Power Button Override	Yes	-
Bus Master Request	Yes	-
Thermal Monitoring	Yes	Yes
USB	Yes	Yes
RTC	Yes	Yes
ACPI Timer	Yes	Yes
GPIO	Yes	Yes
SDATA_IN2 (AC97)	Yes	Yes
IRRX1	Yes	Yes
RI2#	Yes	Yes
GPWIO	Yes	Yes
Internal SMI signal	Yes	-

160 AMD Geode™ SC1200/SC1201 Processor Data Book