AMD SC1201, SC1200 manual BGU481 Ball Assignment Sorted by Ball Number, Configuration

Signal Definitions 32579B

Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number

Ball		I/O	Buffer1	Power
No.	Signal Name	(PU/PD)	Type	Rail	Configuration
A1	VSS	GND	---	---	---
A2	VIO	PWR	---	---	---
A3	AD30	I/O	INPCI,	VIO	Cycle Multiplexed
			OPCI
	D6	I/O	INPCI,
			OPCI
A4	PCICLK0	O	OPCI	VIO	---
	FPCI_MON	I	INSTRP		Strap (See Table 3-
		(PD100)			4 on page 44.)
A5	REQ1#	I	INPCI	VIO	---
		(PU22.5)
A6	PCIRST#	O	OPCI	VIO	---
A7	PCICLK	I	INT	VIO	---
A8	IOW#	O	O3/5	VIO	PMR[21] = 0 and
					PMR[2] = 0
	DOCW#	O	O3/5		PMR[21] = 0 and
					PMR[2] = 1
	GPIO15	I/O	INTS,		PMR[21] = 1 and
		(PU22.5)	O3/5		PMR[2] = 1
A9	GPIO20	I/O	INT, O3/5	VIO	(PMR[23]3 = 0 and
		(PU22.5)			PMR[7] = 0) or
					(PMR[23]3 = 1 and
					PMR[15] = 1 and
					PMR[7] = 0)
	DOCCS#	O	O3/5		(PMR[23]3 = 0 and
		(PU22.5)			PMR[7] = 1) or
					(PMR[23]3 = 1 and
					PMR[15] = 1 and
					PMR[7] = 1)
	TFTD0	O	O1/4		PMR[23]3 = 1 and
		(PU22.5)			PMR[15] = 0
A10	GPIO17	I/O	INTS,	VIO	(PMR[23]3 = 0 and
		(PU22.5)	O3/5		PMR[5] = 0) or
					(PMR[23]3 = 1 and
					PMR[15] = 1 and
					PMR[5] = 0)
	IOCS0#	O	O3/5		(PMR[23]3 = 0 and
		(PU22.5)			PMR[5] = 1) or
					(PMR[23]3 = 1 and
					PMR[15] = 1 and
					PMR[5] = 1)
	TFTDCK	O	O1/4		PMR[23]3 = 1 and
		(PU22.5)			PMR[15] = 0
A11	HSYNC	O	O1/4	VIO	---
A12	AVCCCRT	PWR	---	---	---
A13	VSS	GND	---	---	---
A14	GREEN	O	WIRE	AVC-	---
				CCRT
A15	BLUE	O	WIRE	AVC-	---
				CCRT
A16	VSS	GND	---	---	---
A17	VPLL2	PWR	---	---	---

Ball			I/O	Buffer1	Power
No.		Signal Name	(PU/PD)	Type	Rail	Configuration
A18	6, 2	PD7	I/O	IN ,	V	PMR[23]	3	= 0 and
				T	IO
				O14/14		(PMR[27] = 0 and
						FPCI_MON = 0)
		TFTD13	O	O1/4		PMR[23]3 = 1 and
						(PMR[27] = 0 and
						FPCI_MON = 0)
		F_AD7	O	O14/14		PMR[23]3 = 0 and
						(PMR[27] = 1 or
						FPCI_MON = 1)
A19		VSS	GND	---	---	---
A20	6, 2	PD6	I/O	IN ,	V	PMR[23]	3	= 0 and
				T	IO
				O14/14		(PMR[27] = 0 and
						FPCI_MON = 0)
		TFTD1	O	O1/4		(PMR[23]3 = 1 and
						PMR[15] = 0) and
						(PMR[27] = 0 and
						FPCI_MON = 0
		VOPD0	O	O1/4		(PMR[23]3 = 1 and
						PMR[15] = 1) and
						(PMR[27] = 0 and
						FPCI_MON = 0)
		F_AD6	O	O14/14		PMR[23]3 = 0 and
						(PMR[27] = 1 or
						FPCI_MON = 1)
A21	6, 2	PD1	I/O	IN ,	V	PMR[23]	3	= 0 and
				T	IO
				O14/14		(PMR[27] = 0 and
						FPCI_MON = 0)
		TFTD7	O	O1/4		(PMR[23]3 = 1 and
						PMR[15] = 0) and
						(PMR[27] = 0 and
						FPCI_MON = 0)
		VOPD6	O	O1/4		(PMR[23]3 = 1 and
						PMR[15] = 1) and
						(PMR[27] = 0 and
						FPCI_MON = 0)
		F_AD1	O	O14/14		PMR[23]3 = 0 and
						(PMR[27] = 1 or
						FPCI_MON = 1)
A22	6, 2	STB#/WRITE#	O	O	V	PMR[23]	3	= 0 and
				14/14	IO
						(PMR[27] = 0 and
						FPCI_MON = 0)
		TFTD17	O	O1/4		PMR[23]3 = 1 and
						(PMR[27] = 0 and
						FPCI_MON = 0)
		F_FRAME#	O	O14/14		PMR[23]3 = 0 and
						(PMR[27] = 1 or
						FPCI_MON = 1)
A23		CVBS	O	WIRE	AVCCTV	See F4BAR0+
		Y	O			Memory Offset
						C08h[4:3] bit
		TVG	O			description on
						page 356.
A24		SVY	O	WIRE	AVCCTV	See F4BAR0+
		TVR	O			Memory Offset
						C08h[4:3] bit
		Cb	O			description on
						page 356.
		CVBS	O
A25		TVRSET	I	WIRE	AVCCTV	---
A266		DPOS_PORT3	I/O	INUSB,	AVC-	---
				OUSB	CUSB
A276		DNEG_PORT3	I/O	INUSB,	AVC-	---
				OUSB	CUSB

AMD Geode™ SC1200/SC1201 Processor Data Book 29