AMD SC1201, SC1200 manual Module Architecture, Access, Internal Internal Signals

SuperI/O Module 32579B

5.2Module Architecture

The SIO module comprises a collection of generic func- tional blocks. Each functional block is described in detail later in this chapter. The beginning of this chapter describes the SIO structure and provides all device specific information, including special implementation of generic blocks, system interface and device configuration.

The SIO module is based on eight logical devices, the host interface, and a central configuration register set, all built around a central, internal 8-bit bus.

The host interface serves as a bridge between the external ISA interface and the internal bus. It supports 8-bit I/O read, 8-bit I/O write and 8-bit DMA transactions, as defined in Personal Computer Bus Standard P996.

The central configuration register set supports ACPI com- pliant PnP configuration. The configuration registers are structured as a subset of the Plug and Play Standard Reg- isters, defined in Appendix A of the Plug and Play ISA Specification Version 1.0a by Intel and Microsoft. All sys- tem resources assigned to the functional blocks (I/O address space, DMA channels and IRQ lines) are config- ured in, and managed by, the central configuration register set. In addition, some function-specific parameters are con- figurable through this unit and distributed to the functional blocks through special control signals.

The source of the device internal clocks is the 48 MHz clock signal or through the 32.768 KHz crystal with an internal frequency multiplier. RTC operates on a 32 KHz clock.

IRTX/SOUT3

IRRX1/SIN3

ACK#

Infrared

SIN1

AFD#/DSTRB#

Communication

BUSY/WAIT#

Serial

Port/Serial Port 3

SOUT1

ERR#

INIT#

Parallel

Port 1

PD[7:0]

Port

DTR#/BOUT1

PE

SLCT

SLIN#/ASTRB#

SIN2

STB#/WRITE#

SOUT2

Serial

RTS2#

DTR2#/BOUT2

Port 2

AB1C

ACCESS.

Configuration

CTS2

and Control

RI2#

AB1D

bus 1

DCD2#

Registers

DSR2#

AB2C

TC

ACCESS.

DACK0-3

DRQ0-3

bus 2

Internal

AB2D

IRQ1-12,14-15 Internal

Host

IOCHRDY

Signals

Interface

ZWS#

Real-Time Clock (RTC)

System

IOWR#

Wakeup

IORD#

AEN

InternalBus

ControlSignals

SDATAIN2

PWUREQ

ALARM

X1C/X1

X2C

V

V

RI2#

CONFIG CLKIN MR D[7:0]

A[15:0]

SB

BAT

Internal

Internal Signals

Signal

Figure 5-2. Detailed SIO Block Diagram

AMD Geode™ SC1200/SC1201 Processor Data Book 91