AMD SC1201, SC1200 manual GNT0#

Signal Definitions 32579B

Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)

Ball		I/O	Buffer1	Power
No.	Signal Name	(PU/PD)	Type	Rail	Configuration
C1	AD26	I/O	INPCI,	VIO	Cycle Multiplexed
			OPCI
	D2	I/O	INPCI,
			OPCI
C2	AD24	I/O	INPCI,	VIO	Cycle Multiplexed
			OPCI
	D0	I/O	INPCI,
			OPCI
C3	VIO	PWR	---	---	---
C4	AD25	I/O	INPCI,	VIO	Cycle Multiplexed
			OPCI
	D1	I/O	INPCI,
			OPCI
C5	GNT0#	O	OPCI	VIO	---
	DID0	I	INSTRP		Strap (See Table 3-
		(PD100)			4 on page 44.)
C6	GNT1#	O	OPCI	VIO	---
	DID1	I	INSTRP		Strap (See Table 3-
		(PD100)			4 on page 44.)
C7	VIO	PWR	---	---	---
C8	ROMCS#	O	O3/5	VIO	---
	BOOT16	I	INSTRP	VIO	Strap (See Table 3-
		(PD100)			4 on page 44.)
C9	GPIO19	I/O	INTS,	VIO	PMR[9] = 0 and
		(PU22.5)	O3/5		PMR[4] = 0
	INTC#	I	INTS		PMR[9] = 0 and
		(PU22.5)			PMR[4] = 1
	IOCHRDY	I	INTS1		PMR[9] = 1 and
		(PU22.5)			PMR[4] = 1
C10	VIO	PWR	---	---	---
C11	IRTX	O	O8/8	VIO	PMR[6] = 0
	SOUT3	O	O8/8		PMR[6] = 1
C12	VSSCRT	GND	---	---	---
C13	AVCCCRT	PWR	---	---	---
C14	AVSSCRT	GND	---	---	---
C15	AVSSCRT	GND	---	---	---
C16	AVSSPLL2	GND	---	---	---
C176,2	SLCT	I	INT	VIO	PMR[23]3 = 0 and
					(PMR[27] = 0 and
					FPCI_MON = 0)
	TFTD15	O	O1/4		PMR[23]3 = 1 and
					(PMR[27] = 0 and
					FPCI_MON = 0)
	F_C/BE3#	O	O1/4		PMR[23]3 = 0 and
					(PMR[27] = 1 or
					FPCI_MON = 1)
C18	PD4	I/O	INT,	VIO	PMR[23]3 = 0 and
			O14/14		(PMR[27] = 0 and
					FPCI_MON = 0)
	TFTD10	O	O1/4		PMR[23]3 = 1 and
					(PMR[27] = 0 and
					FPCI_MON = 0)
	F_AD4	O	O14/14		PMR[23]3 = 0 and
					(PMR[27] = 1 or
					FPCI_MON = 1)

Ball		I/O	Buffer1	Power
No.	Signal Name	(PU/PD)	Type	Rail	Configuration
C196,2	PD5	I/O	INT,	VIO	PMR[23]3 = 0 and
			O14/14		(PMR[27] = 0 and
					FPCI_MON = 0)
	TFTD11	O	O1/4		PMR[23]3 = 1 and
					(PMR[27] = 0 and
					FPCI_MON = 0)
	F_AD5	O	O14/14		PMR[23]3 = 0 and
					(PMR[27] = 1 or
					FPCI_MON = 1)
C206,2	PD3	I/O	INT,	VIO	PMR[23]3 = 0 and
			O14/14		(PMR[27] = 0 and
					FPCI_MON = 0)
	TFTD9	O	O1/4		PMR[23]3 = 1 and
					(PMR[27] = 0 and
					FPCI_MON = 0)
	F_AD3	O	O14/14		PMR[23]3 = 0 and
					(PMR[27] = 1 or
					FPCI_MON = 1)
C216,2	PD0	I/O	INT,	VIO	PMR[23]3 = 0 and
			O14/14		(PMR[27] = 0 and
					FPCI_MON = 0)
	TFTD6	O	O1/4		(PMR[23]3 = 1 and
					PMR[15] = 0) and
					(PMR[27] = 0 and
					FPCI_MON = 0)
	VOPD5	O	O1/4		(PMR[23]3 = 1 and
					PMR[15] = 1) and
					(PMR[27] = 0 and
					FPCI_MON = 0)
	F_AD0	O	O14/14		PMR[23]3 = 0 and
					(PMR[27] = 1 or
					FPCI_MON = 1)
C22	VIO	PWR	---	---	---
C23	SVC	O	WIRE	AVCCTV	See F4BAR0+
	Cr	O			Memory Offset
					C08h[4:3] bit
	Cb	O			description on
					page 356.
	TVB	O
	TVR	O
C24	TVREF	I/O	WIRE	AVCCTV	---
C25	VIO	PWR	---	---	---
C26	INTB#	I	INPCI	VIO	---
		(PU22.5)
C27	AVSSUSB	GND	---	---	---
C28	GPIO9	I/O	INTS,	VIO	PMR[18] = 0 and
		(PU22.5)	O1/4		PMR[8] = 0
	DCD2#	I	INTS		PMR[18] = 1 and
		(PU22.5)			PMR[8] = 0
	IDE_IOW1#	O	O1/4		PMR[18] = 0 and
		(PU22.5)			PMR[8] = 1
	SDTEST2	O	O2/5		PMR[18] = 1 and
		(PU22.5)			PMR[8] = 1
C29	VIO	PWR	---	---	---

AMD Geode™ SC1200/SC1201 Processor Data Book 31