Signal Definitions

32579B

Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)

Ball

 

I/O

Buffer1

Power

 

No.

Signal Name

(PU/PD)

Type

Rail

Configuration

 

 

 

 

 

 

N15

VSS

GND

---

---

---

N16

VSS

GND

---

---

---

N17

VSS

GND

---

---

---

N18

VCORE

PWR

---

---

---

N19

VCORE

PWR

---

---

---

N28

VSS

GND

---

---

---

N29

GPIO12

I/O

INAB,

VIO

PMR[19] = 0

 

 

(PU22.5)

O8/8

 

 

 

AB2C

I/O

INAB,

 

PMR[19] = 1

 

 

(PU22.5)

OD8

 

 

N30

AB1D

I/O

INAB,

VIO

PMR[23]3 = 0 or

 

 

(PU22.5)

OD8

 

(PMR[23] = 1 and

 

 

 

 

 

PMR[15] = 1)

 

GPIO1

I/O

INT, O3/5

 

PMR[23]3 = 1 and

 

 

(PU22.5)

 

 

PMR[15] = 0 and

 

 

 

 

 

PMR[13] = 0

 

 

 

 

 

 

 

IOCS1#

O

O3/5

 

PMR[23]3 = 1 and

 

 

 

 

 

PMR[15] = 0 and

 

 

 

 

 

PMR[13] = 1

 

 

 

 

 

 

N31

AB1C

I/O

INAB,

VIO

PMR[23]3 = 0 or

 

 

(PU22.5)

OD8

 

(PMR[23] = 1 and

 

 

 

 

 

PMR[15] = 1)

 

 

 

 

 

 

 

GPIO20

I/O

INT, O3/5

 

PMR[23]3 = 1 and

 

 

(PU22.5)

 

 

PMR[15] = 0 and

 

 

 

 

 

PMR[7] = 0

 

 

 

 

 

 

 

DOCCS#

O

O3/5

 

PMR[23]3 = 1 and

 

 

 

 

 

PMR[15] = 0 and

 

 

 

 

 

PMR[7] = 1

 

 

 

 

 

 

P1

AD4

I/O

INPCI,

VIO

Cycle Multiplexed

 

 

 

OPCI

 

 

 

A4

O

OPCI

 

 

P2

IDE_CS1#

O

O1/4

VIO

PMR[24] = 0

 

TFTDE

O

O1/4

 

PMR[24] = 1

P3

AD1

I/O

INPCI,

VIO

Cycle Multiplexed

 

 

 

OPCI

 

 

 

A1

O

OPCI

 

 

P4

VCORE

PWR

---

---

---

P13

VCORE

PWR

---

---

---

P14

VCORE

PWR

---

---

---

P15

VSS

GND

---

---

---

P16

VSS

GND

---

---

---

P17

VSS

GND

---

---

---

P18

VCORE

PWR

---

---

---

P19

VCORE

PWR

---

---

---

P28

VCORE

PWR

---

---

---

P29

SDATA_OUT

O

OAC97

VIO

---

 

TFT_PRSNT

I

INSTRP

VIO

Strap (See Table 3-

 

 

(PD100)

 

 

4 on page 44.)

P30

SYNC

O

OAC97

VIO

---

 

CLKSEL3

I

INSTRP

 

Strap (See Table 3-

 

 

(PD100)

 

 

4 on page 44.)

P31

AC97_CLK

O

O2/5

VIO

PMR[25] = 1

R1

VSS

GND

---

---

---

R2

VSS

GND

---

---

---

Ball

 

I/O

Buffer1

Power

 

No.

Signal Name

(PU/PD)

Type

Rail

Configuration

 

 

 

 

 

 

R3

VSS

GND

---

---

---

R4

VSS

GND

---

---

---

R13

VSS

GND

---

---

---

R14

VSS

GND

---

---

---

R15

VSS

GND

---

---

---

R16

VSS

GND

---

---

---

R17

VSS

GND

---

---

---

R18

VSS

GND

---

---

---

R19

VSS

GND

---

---

---

R28

VSS

GND

---

---

---

R29

VSS

GND

---

---

---

R30

VSS

GND

---

---

---

R31

VSS

GND

---

---

---

T1

VCORE

PWR

---

---

---

T2

VCORE

PWR

---

---

---

T3

VCORE

PWR

---

---

---

T4

VCORE

PWR

---

---

---

T13

VSS

GND

---

---

---

T14

VSS

GND

---

---

---

T15

VSS

GND

---

---

---

T16

VSS

GND

---

---

---

T17

VSS

GND

---

---

---

T18

VSS

GND

---

---

---

T19

VSS

GND

---

---

---

T28

VCORE

PWR

---

---

---

T29

VCORE

PWR

---

---

---

T30

VCORE

PWR

---

---

---

T31

VCORE

PWR

---

---

---

U1

AD0

I/O

INPCI,

VIO

Cycle Multiplexed

 

 

 

OPCI

 

 

 

A0

O

OPCI

 

 

U2

IDE_ADDR2

O

O1/4

VIO

PMR[24] = 0

 

TFTD4

O

O1/4

 

PMR[24] = 1

U3

AD2

I/O

INPCI,

VIO

Cycle Multiplexed

 

 

 

OPCI

 

 

 

A2

O

OPCI

 

 

U4

VCORE

PWR

---

---

---

U13

VSS

GND

---

---

---

U14

VSS

GND

---

---

---

U15

VSS

GND

---

---

---

U16

VSS

GND

---

---

---

U17

VSS

GND

---

---

---

U18

VSS

GND

---

---

---

U19

VSS

GND

---

---

---

U28

VCORE

PWR

---

---

---

U29

AC97_RST#

O

O2/5

VIO

FPCI_MON = 0

 

F_STOP#

O

O2/5

 

FPCI_MON = 1

AMD Geode™ SC1200/SC1201 Processor Data Book

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AMD SC1201, SC1200 manual GPIO12