AMD SC1201, SC1200 manual Sub-ISA Interface Signals

Signal Definitions 32579B

3.4.8Sub-ISA Interface Signals

Signal Name	Ball No.	Type	Description	Mux
A[23:0]	See	O	Address Lines	AD[23:0]
	Table 3-3
	on page
	40
D15	See	I/O	Data Bus	STOP#
	Table 3-3
D14				IRDY#
	on page
D13				TRDY#
	40
D12				PAR
D11				C/BE3#
D10				C/BE2#
D9				C/BE1#
D8				C/BE0#
D[7:0]				AD[31:24]
BHE#	E4	O	Byte High Enable. With A0, defines byte accessed for	DEVSEL#
			16 bit wide bus cycles.
IOCS1#	D10	O	I/O Chip Selects	GPIO1+TFTD12
	N30			AB1D+GPIO1
IOCS0#	A10			GPIO17+TFTDCK
ROMCS#	C8	O	ROM or Flash ROM Chip Select	BOOT16 (Strap)
DOCCS#	A9	O	DiskOnChip or NAND Flash Chip Select	GPIO20+TFTD0
	N31			AB1C+GPIO20
TRDE#	D11	O	Transceiver Data Enable Control. Active low for Sub-	GPIO0
			ISA data transfers. The signal timing is as follows:
			• In a read cycle, TRDE# has the same timing as RD#.
			• In a write cycle, TRDE# is asserted (to active low) at
			the time WR# is asserted. It continues being asserted
			for one PCI clock cycle after WR# has been negated,
			then it is negated.
RD#	B8	O	Memory or I/O Read. Active on any read cycle.	CLKSEL0 (Strap)
WR#	B9	O	Memory or I/O Write. Active on any write cycle.	---
IOR#	D9	O	I/O Read. Active on any I/O read cycle.	DOCR#+GPIO14
IOW#	A8	O	I/O Write. Active on any I/O write cycle.	DOCW#+GPIO15
DOCR#	D9	O	DiskOnChip or NAND Flash Read. Active on any mem-	IOR#+GPIO14
			ory read cycle to DiskOnChip.
DOCW#	A8	O	DiskOnChip or NAND Flash Write. Active on any mem-	IOW#+GPIO15
			ory write cycle to DiskOnChip.
IRQ9	AA3	I	Interrupt 9 Request Input. Active high.	IDE_DATA6
			Note: If IRQ9 function is selected but not used, tie
			IRQ9 low.
IOCHRDY	C9	I	I/O Channel Ready	GPIO19+INTC#
			Note: If IOCHRDY function is selected but not used, tie
			IOCHRDY high.
AMD Geode™ SC1200/SC1201 Processor Data Book				59