Core Logic Module - ISA Legacy Register Space

32579B

 

 

 

Table 6-45. Programmable Interval Timer Registers (Continued)

Bit

 

Description

 

 

 

 

 

I/O Port 042h

 

 

 

 

 

 

 

Write

 

 

 

PIT Timer 2 Counter (Speaker)

 

 

 

 

7:0

 

Counter Value.

 

 

 

 

 

 

Read

 

 

 

PIT Timer 2 Status (Speaker)

 

 

 

7

 

Counter Output. State of counter output signal.

 

 

 

6

 

Counter Loaded. Indicates if the last count written is loaded.

 

 

0:

Yes.

 

 

 

1:

No.

 

 

 

 

 

5:4

 

Current Read/Write Mode.

 

 

 

00: Counter latch command.

 

 

 

01: R/W LSB only.

 

 

 

10: R/W MSB only.

 

 

 

11: R/W LSB, followed by MSB.

 

 

 

 

 

3:1

 

Current Counter Mode. 0-5.

 

 

 

 

 

0

 

BCD Mode.

 

 

 

0:

Binary.

 

 

 

1: BCD (Binary Coded Decimal).

 

 

 

 

 

 

I/O Port 043h (R/W)

PIT Mode Control Word Register

Notes: 1. If bits [7:6] = 11: Register functions as Read Status Command and:

 

 

Bit 5 = Latch Count

 

 

 

Bit 4 = Latch Status

 

 

 

Bit 3 = Select Counter 2

 

 

 

Bit 2 = Select Counter 1

 

 

 

Bit 1 = Select Counter 0

 

 

 

Bit 0 = Reserved

 

 

2. If bits [5:4] = 00: Register functions as Counter Latch Command and:

 

 

Bits [7:6] = Selects Counter

 

 

 

Bits [3:0] = Don’t care

 

 

 

 

 

7:6

 

Counter Select.

 

 

 

00: Counter 0.

 

 

 

01: Counter 1.

 

 

 

10: Counter 2.

 

 

 

11: Read-back command (Note 1).

 

 

 

 

 

5:4

 

Current Read/Write Mode.

 

 

 

00: Counter latch command.

 

 

 

01: R/W LSB only.

 

 

 

10: R/W MSB only.

 

 

 

11: R/W LSB, followed by MSB.

 

 

 

 

 

3:1

 

Current Counter Mode. 0-5.

 

 

 

 

 

0

 

BCD Mode.

 

 

 

0:

Binary.

 

 

 

1: BCD (Binary Coded Decimal).

 

 

 

 

 

 

AMD Geode™ SC1200/SC1201 Processor Data Book

303

Page 303
Image 303
AMD SC1201, SC1200 manual Bit Description Port 042h Write, Counter Value Read, Current Counter Mode BCD Mode, Port 043h R/W