32579B

List of Figures

Figure 7-6.

Capture Video Mode Weave Example Using Two Video Frame Buffers

. . . . . . . 319

Figure 7-7.

Video Block Diagram

. . . . . . . 320

Figure 7-8.

Horizontal Downscaler Block Diagram

. . . . . . . 321

Figure 7-9.

Linear Interpolation Calculation

. . . . . . . 322

Figure 7-10.

Mixer/Blender Block Diagram

. . . . . . . 323

Figure 7-11.

Graphics/Video Frame with Alpha Windows

. . . . . . . 326

Figure 7-12.

Color Key and Alpha Blending Logic

. . . . . . . 328

Figure 7-13.

TVOUT Block Diagram

. . . . . . . 329

Figure 7-14.

DAC Voltage Levels

. . . . . . . 330

Figure 7-15.

TFT Power Sequence

. . . . . . . 331

Figure 7-16.

PLL Block Diagram

. . . . . . . 332

Figure 9-1.

Differential Input Sensitivity for Common Mode Range

. . . . . . . 374

Figure 9-2.

General Drive level and Measurement Points

. . . . . . . 376

Figure 9-3.

Memory Controller Drive Level and Measurement Points

. . . . . . . 377

Figure 9-4.

Memory Controller Output Valid Timing Diagram

. . . . . . . 379

Figure 9-5.

Read Data In Setup and Hold Timing Diagram

. . . . . . . 379

Figure 9-6.

Video Input Port Timing Diagram

. . . . . . . 380

Figure 9-7.

Video Output Port Timing Diagram

. . . . . . . 381

Figure 9-8.

TFT Timing Diagram

. . . . . . . 382

Figure 9-9.

ACB Signals: Rising and Falling Timing Diagram

. . . . . . . 386

Figure 9-10.

ACB Start and Stop Condition Timing Diagram

. . . . . . . 386

Figure 9-11.

ACB Start Condition TIming Diagram

. . . . . . . 387

Figure 9-12.

ACB Data Bit Timing Diagram

. . . . . . . 387

Figure 9-13.

Testing Setup for PCI Slew Rate and Minimum Timing

. . . . . . . 388

Figure 9-14.

V/I Curves for PCI Output Signals

. . . . . . . 389

Figure 9-15.

PCICLK Timing and Measurement Points

. . . . . . . 390

Figure 9-16.

Load Circuits for PCI Maximum Time Measurements

. . . . . . . 391

Figure 9-17.

PCI Output Timing Measurement Conditions

. . . . . . . 392

Figure 9-18.

PCI Input Timing Measurement Conditions

. . . . . . . 393

Figure 9-19.

PCI Reset Timing

. . . . . . . 393

Figure 9-20.

Sub-ISA Read Operation Timing Diagram

. . . . . . . 396

Figure 9-21.

Sub-ISA Write Operation Timing Diagram

. . . . . . . 397

Figure 9-22.

LPC Output Timing Diagram

. . . . . . . 398

Figure 9-23.

LPC Input Timing Diagram

. . . . . . . 398

Figure 9-24.

IDE Reset Timing Diagram

. . . . . . . 399

Figure 9-25.

Register Transfer to/from Device Timing Diagram

. . . . . . . 401

Figure 9-26.

PIO Data Transfer to/from Device Timing Diagram

. . . . . . . 403

Figure 9-27.

Multiword DMA Data Transfer Timing Diagram

. . . . . . . 405

Figure 9-28.

Initiating an UltraDMA Data in Burst Timing Diagram

. . . . . . . 407

Figure 9-29.

Sustained UltraDMA Data In Burst Timing Diagram

. . . . . . . 408

Figure 9-30.

Host Pausing an UltraDMA Data In Burst Timing Diagram

. . . . . . . 409

Figure 9-31.

Device Terminating an UltraDMA Data In Burst Timing Diagram

. . . . . . . 410

Figure 9-32.

Host Terminating an UltraDMA Data In Burst Timing Diagram

. . . . . . . 411

Figure 9-33.

Initiating an UltraDMA Data Out Burst Timing Diagram

. . . . . . . 412

Figure 9-34.

Sustained UltraDMA Data Out Burst Timing Diagram

. . . . . . . 413

Figure 9-35.

Device Pausing an UltraDMA Data Out Burst Timing Diagram

. . . . . . . 414

Figure 9-36.

Host Terminating an UltraDMA Data Out Burst Timing Diagram

. . . . . . . 415

Figure 9-37.

Device Terminating an UltraDMA Data Out Burst Timing Diagram

. . . . . . . 416

Figure 9-38.

USB Data Signal Rise and Fall Timing Diagram

. . . . . . . 419

Figure 9-39.

USB Source Differential Data Jitter Timing Diagram

. . . . . . . 419

Figure 9-40.

USB EOP Width Timing Diagram

. . . . . . . 420

Figure 9-41.

USB Receiver Jitter Tolerance Timing Diagram

. . . . . . . 420

Figure 9-42.

UART, Sharp-IR, SIR, and Consumer Remote Control Timing Diagram

. . . . . . . 421

Figure 9-43.

Fast IR Timing (MIR and FIR) Diagram

. . . . . . . 422

Figure 9-44.

Standard Parallel Port Typical Data Exchange Timing Diagram

. . . . . . . 423

6

AMD Geode™ SC1200/SC1201 Processor Data Book

Page 6
Image 6
AMD SC1200 319, 374, General Drive level and Measurement Points 376, 377, 379, 403, 407, 408, 409, 410, 411, 414, 415, 416