AMD SC1201, SC1200 manual Default Configuration Setup, Address Decoding

SuperI/O Module 32579B

Write accesses to unimplemented registers (i.e., accessing the Data register while the Index register points to a non- existing register or the LDN is 07h or higher than 08h), are ignored and a read returns 00h on all addresses except for 74h and 75h (DMA configuration registers) which returns 04h (indicating no DMA channel is active). The configura- tion registers are accessible immediately after reset.

5.3.3Default Configuration Setup

The device has four reset types:

Software Reset

This reset is generated by bit 1 of the SIOCF1 register, which resets all logical devices. A software reset also resets most bits in the SIO Configuration and Control regis- ters (see Section 5.4.1 on page 97 for the bits not affected). This reset does not affect register bits that are locked for write access.

Hardware Reset

This reset is activated by the system reset signal. This resets all logical devices, with the exception of the RTC and the SWC, and all SIO Configuration and Control registers, with the exception of the SIOCF2 register. It also resets all SuperI/O control and configuration registers, except for those that are battery-backed.

VPP Power-Up Reset

This reset is activated when either VSB or VBAT is powered on after both have been off. VPP is an internal voltage which is a combination of VSB and VBAT. VPP is taken from VSB if VSB is greater than the minimum (Min) value defined in Section 9.1.4 "Operating Conditions" on page 366; oth- erwise, VBAT is used as the VPP source. This reset resets all registers whose values are retained by VPP.

VSB Power-Up Reset

This is an internally generated reset that resets the SWC, excluding those SWC registers whose values are retained by VPP. This reset is activated after VSB is powered up.

The SIO module wakes up with the default setup, as fol- lows:

•When a hardware reset occurs:

—The configuration base address is 2Eh, 15Ch or None, according to the IO_SIOCFG_IN bit values, as shown in Table 5-1 on page 92.

—All Logical devices are disabled, with the exception of the RTC and the SWC, which remains functional but whose registers cannot be accessed.

•When either a hardware or a software reset occurs:

—The legacy devices are assigned with their legacy system resource allocation.

—The AMD proprietary functions are not assigned with any default resources and the default values of their base addresses are all 00h.

5.3.4Address Decoding

A full 16-bit address decoding is applied when accessing the configuration I/O space, as well as the registers of the functional blocks. However, the number of configurable bits in the base address registers vary for each device.

The lower 1, 2, 3 or 4 address bits are decoded within the functional block to determine the offset of the accessed register, within the device’s I/O range of 2, 4, 8 or 16 bytes, respectively. The rest of the bits are matched with the base address register to decode the entire I/O range allocated to the device. Therefore the lower bits of the base address register are forced to 0 (RO), and the base address is forced to be 2, 4, 8 or 16 byte aligned, according to the size of the I/O range.

The base address of the RTC, Serial Port 1, Serial Port 2, and the Infrared Communication Port are limited to the I/O address range of 00h to 7Fxh only (bits [15:11] are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h. The addresses of the non- legacy devices are configurable within the full 16-bit address range (up to FFFxh).

In some special cases, other address bits are used for internal decoding (such as 10 in the Parallel Port). For more details, please see the detailed description of the base address register for each specific logical device.

AMD Geode™ SC1200/SC1201 Processor Data Book 93