AMD SC1200 IDE UltraDMA Data Burst Timing Parameters, Mode Symbol Parameter Min Max Unit Comments

32579BElectrical Specifications

Table 9-30. IDE UltraDMA Data Burst Timing Parameters

		Mode 0		Mode 1		Mode 2
Symbol	Parameter	Min	Max	Min	Max	Min	Max	Unit	Comments
t2CYC	Typical sustained average two cycle time	240		160		120		ns
	Two cycle time allowing for clock variations	235		156		117		ns
	(from rising edge to next rising edge or from
	falling edge to next falling edge of STROBE)
tCYC	Cycle time allowing for asymmetry and clock	114		75		55		ns
	variations (from STROBE edge to STROBE
	edge)
tDS	Data setup time (at recipient)	15		10		7		ns
tDH	Data hold time (at recipient)	5		5		5		ns
tDVS	Data valid setup time at sender (from data	70		48		34		ns
	bus being valid until STROBE edge)
tDVH	Data valid hold time at sender (from	6		6		6		ns
	STROBE edge until data may become
	invalid)
tFS	First STROBE time (for device to first negate	0	230	0	200	0	170	ns
	IDE_IRDY[0:1] (DSTROBE[0:1]) from
	IDE_IOW[0:1]# (STOP[0:1]) during a data in
	burst)
tLI	Limited interlock time	0	150	0	150	0	150	ns	Note 1
tMLI	Interlock time with minimum	20		20		20		ns	Note 1
tUI	Unlimited interlock time	0		0		0		ns	Note 1
tAZ	Maximum time allowed for output drivers to		10		10		10	ns
	release (from being asserted or negated)
tZAH	Minimum delay time required for output driv-	20		20		20		ns
	ers to assert or negate (from released state)
tZAD		0		0		0		ns
tENV	Envelope time (from IDE_DACK[0:1]# to	20	70	20	70	20	70	ns
	IDE_IOW[0:1]# (STOP[0:1]) and
	IDE_IOR[0:1]# (HDMARDY[0:1]#) during
	data out burst initiation)
tSR	STROBE to DMARDY time (if DMARDY# is		50		30		20	ns
	negated before this long after STROBE
	edge, the recipient receives no more than
	one additional data WORD)
tRFS	Ready-to-final-STROBE time (no STROBE		75		60		50	ns
	edges are sent this long after negation of
	DMARDY#)
tRP	Ready-to-pause time (time that recipient	160		125		100		ns
	waits to initiate pause after negating
	DMARDY#)
tIORDYZ	Pull-up time before allowing IDE_IORDY[0:1]		20		20		20	ns
	to be released
tZIORDY	Minimum time device waits before driving	0		0		0		ns
	IDE_IORDY[0:1]
tACK	Setup and hold times for IDE_DACK[0:1]#	20		20		20		ns
	(before assertion or negation)
tSS	Time from STROBE edge to negation of	50		50		50		ns
	IDE_DREQ[0:1] or assertion of
	IDE_IOW[0:1]# (STOP[0:1]) (when sender
	terminates a burst)

Note 1. tUI, tMLI, and tLI indicate sender-to-recipient or recipient-to-sender interlocks, that is, one agent (either sender or recipient) is wait- ing for the other agent to respond with a signal before proceeding. tUI is an unlimited interlock with no maximum time value. tMLI is a limited timeout with a defined minimum. tLI is a limited time-out with a defined maximum.

406 AMD Geode™ SC1200/SC1201 Processor Data Book