AMD SC1200 Peripheral Power Management, Device Idle Timers and Traps, General Purpose Timers, 164

32579B Core Logic Module

6.2.10.3 Peripheral Power Management

The Core Logic module provides peripheral power man- agement using a combination of device idle timers, address traps, and general purpose I/O pins. Idle timers are used in conjunction with traps to support powering down peripheral devices.

Device Idle Timers and Traps

Idle timers are used to power manage a peripheral by determining when the peripheral has been inactive for a specified period of time, and removing power from the peripheral at the end of that time period.

Idle timers are provided for the commonly-used peripherals (FDC, IDE, Parallel/Serial Ports, and Mouse/Keyboard). In addition, there are three user-defined timers that can be configured for either I/O or memory ranges.

The idle timers are 16-bit countdown timers with a one sec- ond timebase or prescaler, providing a timeout range of 1 to 65536 seconds (1092 minutes) (18 hours). The input clock is 32 KHz. Very small count values have some error since the prescaler is free-running. (See the next subsec- tion "General Purpose Timers" for further discussion on prescaler value limitations.)

When the idle timer count registers are loaded with a non- zero value and enabled, the timers decrement until one of two possibilities happens: a bus cycle occurs at that I/O or memory range, or the timer decrements to zero.

If a bus cycle occurs, the timer is reloaded and begins dec- rementing again. If the timer decrements to zero, and power management is enabled (F0 Index 80h[0] = 1), the timer generates an SMI.

When an idle timer generates an SMI, the SMI handler manages the peripheral power, disables the timer, and enables the trap. The next time an event occurs, the trap generates an SMI. This time, the SMI handler applies power to the peripheral, resets the timer, and disables the trap.

Relevant registers for controlling Device Idle Timers are: F0 Index 80h, 81h, 82h, 93h, 98h-9Eh, and ACh.

Relevant registers for controlling User Defined Device Idle Timers are: F0 Index 81h, 82h, A0h, A2h, A4h, C0h, C4h, C8h, CCh, CDh, and CEh.

Although not considered as device idle timers, two addi- tional timers are provided by the Core Logic module. The Video Idle Timer used for Suspend-determination and the VGA Timer used for SoftVGA.

The programming bits for these timers are:

•F0 Index 81h[7], Video Access Idle Timer Enable

•F0 Index 82h[7], Video Access Trap Enable

•F0 Index A6h[15:0], Video Timer Count

•F0 Index 83h[3], VGA Timer Enable

•F0 Index 8Bh[6], VGA Timer Base

•F0 Index 8Eh[7:0], VGA Timer Count

General Purpose Timers

The Core Logic module contains two general purpose idle timers, General Purpose Timer 1 (F0 Index 88h) and Gen- eral Purpose Timer 2 (F0 Index 8Ah). These two timers are similar to the Device Idle Timers in that they count down to zero unless re-triggered, and generate an SMI when they reach zero. However, these are 8-bit timers instead of 16 bits, they have a programmable timebase, and the events which reload these timers are configurable. These timers are typically used for an indication of system inactivity for Suspend determination.

General Purpose Timer 1 can be re-triggered by activity to any of the configured User Defined Devices, Keyboard and Mouse, Parallel and Serial, Floppy disk, or Hard disk.

General Purpose Timer 2 can be re-triggered by a transi- tion on the GPIO7 signal (if GPIO7 is properly configured).

When a General Purpose Timer is enabled or when an event reloads the timer, the timer is loaded with the config- ured count value. Upon expiration of the timer an SMI is generated and a status flag is set. Once expired, this counter must be re-initialized by disabling and enabling it.

The timebase or prescaler for both General Purpose Tim- ers can be configured as either 1 second (default) or 1 mil- lisecond. The 32 KHz clock feeds the prescaler. The registers at F0 Index 89h and 8Bh are the control registers for the General Purpose Timers.

The prescaler (1 millisecond or 1 second) that feeds the timers is free-running; meaning that the first count decre- ment will not be correct. The decrement time can be as short as 0 or as long as the prescaler. The actual time for the decrement to occur can not be determined since the current prescaler value can not be read. A periodic timer can be achieved after the first timer SMI, because when retriggered, the prescaler will be at or very nearly at the maximum value. Any software using these timers must understand this limitation. Small count values have the most error with a value of 1having the largest error.

ACPI Timer Register

The ACPI Timer register (F1BAR0+I/O Offset 1Ch or at F1BAR1+I/O Offset 1Ch) provides the ACPI counter. The counter counts at 14.31818/4 MHz (3.579545 MHz). If SMI generation is enabled (F0 Index 83h[5] = 1), an SMI or SCI is generated when bit 23 toggles.

164 AMD Geode™ SC1200/SC1201 Processor Data Book