32579B

Signal Definitions

Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)

Ball

 

I/O

Buffer1

Power

 

No.

Signal Name

(PU/PD)

Type

Rail

Configuration

 

 

 

 

 

 

C30

GPIO7

I/O

INTS,

VIO

PMR[17] = 0 and

 

 

(PU22.5)

O1/4

 

PMR[8] = 0

 

RTS2#

O

O1/4

 

PMR[17] = 1 and

 

 

(PU22.5)

 

 

PMR[8] = 0

 

IDE_DACK1#

O

O1/4

 

PMR[17] = 0 and

 

 

(PU22.5)

 

 

PMR[8] = 1

 

SDTEST0

O

O2/5

 

PMR[17] = 1 and

 

 

(PU22.5)

 

 

PMR[8] = 1

C31

GPIO8

I/O

INTS,

VIO

PMR[17] = 0 and

 

 

(PU22.5)

O8/8

 

PMR[8] = 0

 

CTS2#

I

INTS

 

PMR[17] = 1 and

 

 

(PU22.5)

 

 

PMR[8] = 0

 

IDE_DREQ1

I

INTS1

 

PMR[17] = 0 and

 

 

(PU22.5)

 

 

PMR[8] = 1

 

SDTEST4

O

O2/5

 

PMR[17] = 1 and

 

 

(PU22.5)

 

 

PMR[8] = 1

D1

AD21

I/O

INPCI,

VIO

Cycle Multiplexed

 

 

 

OPCI

 

 

 

A21

O

OPCI

 

 

D2

AD22

I/O

INPCI,

VIO

Cycle Multiplexed

 

 

 

OPCI

 

 

 

A22

O

OPCI

 

 

D3

AD20

I/O

INPCI,

VIO

Cycle Multiplexed

 

 

 

OPCI

 

 

 

A20

O

OPCI

 

 

D4

AD27

I/O

INPCI,

VIO

Cycle Multiplexed

 

 

 

OPCI

 

 

 

D3

I/O

INPCI,

 

 

 

 

 

OPCI

 

 

D5

AD31

I/O

INPCI,

VIO

Cycle Multiplexed

 

 

 

OPCI

 

 

 

D7

I/O

INPCI,

 

 

 

 

 

OPCI

 

 

D6

PCICLK1

O

OPCI

VIO

---

 

LPC_ROM

I

INSTRP

 

Strap (See Table 3-

 

 

(PD100)

 

 

4 on page 44.)

D7

VSS

GND

---

---

---

D8

FRAME#

I/O

INPCI,

VIO

---

 

 

(PU22.5)

OPCI

 

 

D9

IOR#

O

O3/5

VIO

PMR[21] = 0 and

 

 

 

 

 

PMR[2] = 0

 

DOCR#

O

O3/5

 

PMR[21] = 0 and

 

 

 

 

 

PMR[2] = 1

 

GPIO14

I/O

INTS,

 

PMR[21] = 1 and

 

 

(PU22.5)

O3/5

 

PMR[2] = 1

D10

GPIO1

I/O

INT, O3/5

VIO

(PMR[23]3 = 0 and

 

 

(PU22.5)

 

 

PMR[13] = 0) or

 

 

 

 

 

(PMR[23]3 = 1 and

 

 

 

 

 

PMR[15] = 1 and

 

 

 

 

 

PMR[13] = 0)

 

 

 

 

 

 

 

IOCS1#

O

O3/5

VIO

(PMR[23]3 = 0 and

 

 

(PU22.5)

 

 

PMR[13] = 1) or

 

 

 

 

 

(PMR[23]3 = 1 and

 

 

 

 

 

PMR[15] = 1 and

 

 

 

 

 

PMR[13] = 1)

 

 

 

 

 

 

 

TFTD12

O

O1/4

VIO

PMR[23]3 = 1 and

 

 

(PU22.5)

 

 

PMR[15] = 0

Ball

 

I/O

Buffer1

Power

 

 

 

No.

Signal Name

(PU/PD)

Type

Rail

Configuration

 

 

 

 

 

 

D11

TRDE#

O

O3/5

VIO

PMR[12] = 0

 

GPIO0

I/O

INTS,

VIO

PMR[12] = 1

 

 

(PU22.5)

O3/5

 

 

 

 

D12

VCCCRT

PWR

---

 

---

---

 

 

D13

VSS

GND

---

 

---

---

 

 

D14

VIO

PWR

---

 

---

---

 

 

D15

AVCCCRT

PWR

---

 

---

---

 

 

D16

VREF

I/O

WIRE

AVC-

---

 

 

 

 

 

 

 

 

CCRT

 

 

 

 

 

 

 

 

 

 

 

 

 

6, 2

PE

I

IN

T

 

V

PMR[23]

3

= 0 and

D17

 

(PU22.5

 

 

IO

 

 

 

 

 

 

 

(PMR[27] = 0 and

 

 

PD22.5)

 

 

 

 

FPCI_MON = 0)

 

 

 

 

 

 

 

(PU/PD under soft-

 

 

 

 

 

 

 

ware control.)

 

 

 

 

 

 

 

TFTD14

O

O1/4

 

PMR[23]3 = 1 and

 

 

 

 

 

 

 

(PMR[27] = 0 and

 

 

 

 

 

 

 

FPCI_MON = 0)

 

 

 

 

 

 

 

F_C/BE2#

O

O1/4

 

PMR[23]3 = 0 and

 

 

 

 

 

 

 

(PMR[27] = 1 or

 

 

 

 

 

 

 

FPCI_MON = 1)

 

 

 

 

 

 

 

 

 

D18

VIO

PWR

---

 

---

---

 

 

D19

VSS

GND

---

 

---

---

 

 

6, 2

PD2

I/O

IN ,

V

PMR[23]

3

= 0 and

D20

 

 

T

 

IO

 

 

 

 

O14/14

 

(PMR[27] = 0 and

 

 

 

 

 

 

 

FPCI_MON = 0)

 

TFTD8

O

O1/4

 

(PMR[23]3 = 1 and

 

 

 

 

 

 

 

PMR[15] = 0) and

 

 

 

 

 

 

 

(PMR[27] = 0 and

 

 

 

 

 

 

 

FPCI_MON = 0)

 

 

 

 

 

 

 

VOPD7

O

O1/4

 

(PMR[23]3 = 1 and

 

 

 

 

 

 

 

PMR[15] = 1) and

 

 

 

 

 

 

 

(PMR[27] = 0 and

 

 

 

 

 

 

 

FPCI_MON = 0)

 

 

 

 

 

 

 

F_AD2

O

O14/14

 

PMR[23]3 = 0 and

 

 

 

 

 

 

 

(PMR[27] = 1 or

 

 

 

 

 

 

 

FPCI_MON = 1)

 

 

 

 

 

 

 

 

 

6, 2

ERR#

I

IN , O

1/4

V

PMR[23]

3

= 0 and

D21

 

 

T

 

IO

 

 

 

 

 

 

 

 

(PMR[27] = 0 and

 

 

 

 

 

 

 

FPCI_MON = 0)

 

 

 

 

 

 

 

TFTD4

O

O1/4

 

(PMR[23]3 = 1 and

 

 

 

 

 

 

 

PMR[15] = 0) and

 

 

 

 

 

 

 

(PMR[27] = 0 and

 

 

 

 

 

 

 

FPCI_MON = 0)

 

 

 

 

 

 

 

VOPD3

O

O1/4

 

(PMR[23]3 = 1 and

 

 

 

 

 

 

 

PMR[15] = 1) and

 

 

 

 

 

 

 

(PMR[27] = 0 and

 

 

 

 

 

 

 

FPCI_MON = 0)

 

 

 

 

 

 

 

F_C/BE0#

O

O1/4

 

PMR[23]3 = 0 and

 

 

 

 

 

 

 

(PMR[27] = 1 or

 

 

 

 

 

 

 

FPCI_MON = 1)

 

 

 

 

 

 

 

 

 

 

32

AMD Geode™ SC1200/SC1201 Processor Data Book

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