Core Logic Module - IDE Controller Registers - Function 2

32579B

Table 6-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration (Continued)

Bit

 

Description

 

 

 

 

 

 

Index 48h-4Bh

Channel 0 Drive 1 PIO Register (R/W)

Reset Value: 00009172h

Channel 0 Drive 1 Programmed I/O Control Register. See F2 Index 40h for bit descriptions.

 

 

 

 

Index 4Ch-4Fh

Channel 0 Drive 1 DMA Control Register (R/W)

Reset Value: 00077771h

Channel 0 Drive 1 MDMA/UDMA Control Register. See F2 Index 44h for bit descriptions.

 

Note:

The PIO Mode format is selected in F2 Index 44h[31], bit 31 of this register is defined as reserved.

 

 

 

 

Index 50h-53h

Channel 1 Drive 0 PIO Register (R/W)

Reset Value: 00009172h

Channel 1 Drive 0 Programmed I/O Control Register. See F2 Index 40h for bit descriptions.

 

 

 

 

Index 54h-57h

Channel 1 Drive 0 DMA Control Register (R/W)

Reset Value: 00077771h

Channel 1 Drive 0 MDMA/UDMA Control Register. See F2 Index 44h for bit descriptions.

 

Note:

The PIO Mode format is selected in F2 Index 44h[31], bit 31 of this register is defined as reserved.

 

 

 

 

Index 58h-5Bh

Channel 1 Drive 1 PIO Register (R/W)

Reset Value: 00009172h

Channel 1 Drive 1 Programmed I/O Control Register. See F2 Index 40h for bit descriptions.

 

 

 

 

Index 5Ch-5Fh

Channel 1 Drive 1 DMA Control Register (R/W)

Reset Value: 00077771h

Channel 1 Drive 1 MDMA/UDMA Control Register. See F2 Index 44h for bit descriptions.

 

Note:

The PIO Mode format is selected in F2 Index 44h[31], bit 31 of this register is defined as reserved.

 

 

 

 

Index 60h-FFh

Reserved

Reset Value: 00h

 

 

 

 

 

AMD Geode™ SC1200/SC1201 Processor Data Book

259

Page 259
Image 259
AMD SC1201, SC1200 manual Bit Description Index 48h-4Bh, Index 50h-53h, Index 58h-5Bh, Index 60h-FFh