Publication ID 32579B
AMD Geode SC1200/SC1201 Processor Data Book
Advanced Micro Devices, Inc. All rights reserved
Contacts Trademarks
Contents
Core Logic Module
Electrical Specifications
Package Specifications
Video Processor Module
Typical Battery Current Normal Operation Mode
Power Supply Connections
Typical Battery Configuration
ACCESS.bus Data Transaction
USB EOP Width Timing Diagram 420
Multiword DMA Data Transfer Timing Diagram 405
USB Data Signal Rise and Fall Timing Diagram 419
Fast IR Timing MIR and FIR Diagram 422
426
424
425
427
32579B
ACB1 and ACB2 Configuration Register
IRCP/SP3 Configuration Register
Serial Ports 1 and 2 Configuration Register
Parallel Port Configuration Register
166
Banks 0 and 1 Common Control and Status Registers 118
119
167
F2BAR4+I/O Offset IDE Controller Configuration Registers
Pciusb USB PCI Configuration Register Summary
F0BAR0+I/O Offset Gpio Configuration Registers
F3 PCI Header Registers for Audio Configuration
402
384
400
404
Core Logic
General Description
Video Processor
SuperI/O
GX1 Processor Module
Features
General Features
Video Processor Module
Nand Eeprom
Other Features
Core Logic Module
SuperI/O Module
32579B
Architecture Overview 32579B
GX1 Module
Memory Controller
SC1200/SC1201 Processor Memory Controller Registers
Width Memory Offset Bits Type Name/Function Reset Value
SC1200/SC1201 Processor Memory Controller Register Summary
MCMEMCNTRL2 R/W
Rsvd Reserved. Write as 0070h
Bit Description GXBASE+8408h-840Bh
Mcbankcfg R/W
Rsvd Reserved. Write as GXBASE+840Ch-840Fh
Mcdracc R/W
Mcgbaseadd R/W
Mcdradd R/W
1 GX1 Module Interface
Fast-PCI Bus
Display
Video Input Port
Power-On Reset
Clock, Timers, and Reset Logic
Reset Logic
System Reset
32579B
SC1200/SC1201
Signal Definitions 32579B
AMD Geode
Processor
USB
Jtag Interface
Signal Definitions Legend
Mnemonic Definition
SC1200/SC1201
Configuration
BGU481 Ball Assignment Sorted by Ball Number
REQ0#
GNT0#
GPIO7
AFD#/DSTRB#
PAR
GPIO12
FTRDY#
AC1 IDEDATA1
Buffer1 Power Signal Name
Ball Buffer Power Signal Name
BGU481 Ball Assignment Sorted Alphabetically by Signal Name
Signal Name Ball No
C11
F30
FC/BE0# D21
FC/BE1# B17
MD25 AC28
MD23
MD24
MD26 AC29
A2, A30, B2, B13
C24
N13, N14, N18
F31
Strap Options
Nominal External PU/PD Strap Settings
Strap Options
Default Alternate Ball No Signal Configuration
Multiplexing Configuration
Two-Signal/Group Multiplexing
TFT, CRT, PCI, GPIO, System
AC97 Fpci Monitoring
ACCESS.bus
Internal Test
Three-Signal/Group Multiplexing
Four-Signal/Group Multiplexing
Gpio UART2 IDE2
Maximum Core Clock Multiplier. These strap signals
Signal Descriptions
Signal Name Ball No Type Description Mux
Boot ROM is 16 Bits Wide. This strap signal enables
Memory Interface Signals
Column Address Strobe. RAS#, CAS#, WE# and CKE
Video Port Interface Signals
4 CRT/TFT Interface Signals
Digital RGB Data to TFT
Current Compensation for TV DAC. a 0.1 µF to 1.2 µF
TV Interface Signals
Super Video Chrominance. S-Video chrominance sig
ACCESS.bus Interface Signals
PCI Bus Interface Signals
INTC#
INTA#
INTB#
INTD# AA2
DEVSEL#
STOP#
LOCK#
BHE#
REQ1#
PERR#
SERR#
REQ0#
Sub-ISA Interface Signals
Low Pin Count LPC Bus Interface Signals
IDE Interface Signals
Universal Serial Bus USB Interface Signals
Serial Ports UARTs Interface Signals
Parallel Port Interface Signals
Fast Infrared IR Port Interface Signals
General Purpose Wakeup I/Os. These signals each
15 AC97 Audio Interface Signals
Power Management Interface Signals
Serial Bus Synchronization. This bit is asserted to syn
PWRCNT1 AK6
Suspend Power Plane Control 1 and 2. Control signal
PWRBTN# AH5
PWRCNT2 AL7
Gpio Interface Signals
Fast-PCI Bus Monitoring Signals. When enabled, this
Debug Monitoring Interface Signals
Jtag Interface Signals
System Management Interrupt. This is the input to
Memory Internal Test Signals. These signals are used
Test and Measurement Interface Signals
PLL6, PLL5 and PLL2 Bypass. These signals are used
Thermal Diode Positive / Negative. These signals are for
Power and Ground Connections1
General Configuration Block 32579B
Configuration Block Addresses
General Configuration Block Register Summary
Width Offset Bits
PMR27
Ball # Internal Test Signals Name Add’l Dependencies
Other Signal Add’l Dependencies
Fpcimon
General Configuration Block
Ball # IDE Signals CRT, Gpio and TFT Signals Name
PP/ACB1/FPCI TFT/VOP
Name Add’l Dependencies
Ball # Gpio Signals LPC Signals Name Add’l Dependencies
32579BGeneral Configuration Block
Reserved
General Configuration Block
Offset 3Dh Revision Register REV RO
Offset 3Eh-3Fh Configuration Base Address Register CBA RO
Offset 38h Interrupt Selection Register Intsel R/W
Watchdog Timer
Functional Description
3describes the Watchdog registers
Watchdog Registers
Watchdog Interrupt
Usage Hints
Watchdog Status Register Wdsts R/WC Reset Value 00h
High-Resolution Timer
High-Resolution Timer Registers
Offset 05h-07h
Tmen Timer Interrupt Enable
Reset Value xxxxxxxxh
Tmclksel Timer Clock Select
Bit Description Offset 08h-0Bh
Clock Generators and PLLs
Component Parameters Values Tolerance
1 27 MHz Crystal Oscillator
Crystal Oscillator Circuit Components
Core Clock Frequency
2 GX1 Module Core Clock
Internal Fast-PCI Clock
Strapped Core Clock Frequency
Video Processor Clocks
SuperI/O Clocks
Core Logic Module Clocks
Clock generator and PLL registers are described in Table
Clock Generator Configuration
Clock Registers
33.3 MHz
1514
Reserved. Must be set to 1110
66.7 MHz
AB1C AB1D AB2C AB2D
Outstanding Features
ISA
Serial Port
PC98 and Acpi Compliant
Parallel Port
Serial Port 3 / Infrared IR Communication Port
Internal Internal Signals
Access
Signals
Module Architecture
Index-Data Register Pair
Configuration Structure / Access
SIO Configuration Options
LDN Assignments
Default Configuration Setup
Address Decoding
Logical Device Control and Configuration Registers
Standard Configuration Registers
SIO Control and Configuration Registers
Standard Logical Device Configuration Registers
Standard Configuration Registers
DMA Channel Select 1 R/W
Index F0h-FEh Logical Device Configuration R/W
32579BSuperI/O Module
Index Type Name Power Rail Reset Value
SIO Control and Configuration Registers
SIO Control and Configuration Register Map
SID. SIO ID
Logical Device Control and Configuration
Relevant RTC Configuration Registers
RTC Configuration Registers
Base Address MSB register
Relevant SWC Registers
LDN 01h System Wakeup Control
10. IRCP/SP3 Configuration Register
Relevant IRCP/SP3 Registers
11. Relevant Serial Ports 1 and 2 Registers
12. Serial Ports 1 and 2 Configuration Register
Serial Ports 1 and 2 Configuration register
LDN 03h and 08h Serial Ports 1
ACB1 and ACB2 Configuration register
14. ACB1 and ACB2 Configuration Register
LDN 05h and 06h ACCESS.bus Ports 1
13. Relevant ACB1 and ACB2 Registers
16. Parallel Port Configuration Register
15. Relevant Parallel Port Registers
Bus Interface RTC Clock Generation
X32I External X32O Battery = 0.1 μF
Real-Time Clock RTC
17. Crystal Oscillator Circuit Components
Oscillator Startup
Signal Parameters
External Elements
External Oscillator
Daylight Saving
Alarms
Timekeeping Data Format
Leap Years
Power Supply
18. System Power States
110
Battery-Backed RAMs and Registers
Interrupt Handling
20. RTC Registers
RTC Registers
19. RTC Register Map
Index Type Name
CRD is
Index 05h Hours Alarm Register Hora R/W
Index 04h Hours Register HOR R/W
112
Index Programmable Century Register CEN R/W
Index Programmable Month Alarm Register Mona R/W
Index 0Ch RTC Control Register C CRC RO
AMD Geode SC1200/SC1201 Processor Data Book 113
23. BCD and Binary Formats
21. Divider Chain Control / Test Selection
22. Periodic Interrupt Rate Encoding
Parameter BCD Format Binary Format
RTC General-Purpose RAM Map 24. Standard RAM Map
0Eh 7Fh Battery-backed general-purpose Byte RAM
00h 7Fh Battery-backed general-purpose Byte RAM
25. Extended RAM Map
26. Time Range Limits for Ceir Protocols
System Wakeup Control SWC
Event Detection
Type Name Value
SWC Registers
27. Banks 0 and 1 Common Control and Status Register Map
Offset Type Name Value
29. Banks 0 and 1 Common Control and Status Registers
30. Bank 1 Ceir Wakeup Configuration and Control Registers
Ceir Pulse Change, Range 1, High Limit
Bit Description Ceir Wakeup Range 1 Registers
Bank 1, Offset 0Ah IRWTR1L Register R/W
Ceir Wakeup Range 2 Registers
ABD ABC
ACCESS.bus Interface
Data Transactions
AMD Geode SC1200/SC1201 Processor Data Book 121
ABC ACK
Acknowledge ACK Cycle
ABD MSB
Arbitration on the Bus
Master Mode
Acknowledge After Every Byte Rule
Addressing Transfer Formats
Master Receive
Sending the Address Byte
Master Transmit
Master Stop
Slave Mode
Configuration
32. ACB Registers
ACB Registers
31. ACB Register Map
MASTER. RO
EN Enable
Reserved Inten Interrupt Enable
Saen Slave Address Enable
Stop Stop
33. Parallel Port Register Map for First Level Offset
Legacy Functional Blocks
Parallel Port
34. Parallel Port Register Map for Second Level Offset
130
35. Parallel Port Bit Map for First Level Offset
36. Parallel Port Bit Map for Second Level Offset
Uart Functionality SP1 and SP2
Type Name
40. Bank 2 Register Map
38. Bank Selection Encoding
39. Bank 1 Register Map
41. Bank 3 Register Map
Register Bits
42. Bank 0 Bit Map
43. Bank 1 Bit Map
Register Bits Offset
134
44. Bank 2 Bit Map
45. Bank 3 Bit Map
IRCP/SP3 Register and Bit Maps
3.1 IR/SP3 Mode Register Bank Overview
46. Bank 0 Register Map
01h Register Throughout Offset 00h All Banks
49. Bank 2 Register Map
47. Bank Selection Encoding
48. Bank 1 Register Map
BSR Bits Bank Selected Functionality
52. Bank 5 Register Map
50. Bank 3 Register Map
51. Bank 4 Register Map
55. Bank 0 Bit Map
53. Bank 6 Register Map
54. Bank 7 Register Map
58. Bank 3 Bit Map
56. Bank 1 Bit Map
57. Bank 2 Bit Map
59. Bank 4 Bit Map
62. Bank 7 Bit Map
60. Bank 5 Bit Map
61. Bank 6 Bit Map
Feature List
Video Processor Interface
Config
Integrated Audio
Low Pin Count LPC Interface
Fast-PCI Interface to External PCI Bus
Pserial Interface
IDE Controller
IDE Configuration Registers
PIO Mode
Video Retrace Interrupt
Physical Region Descriptor Format
Stop
UltraDMA/33 Signal Definitions
UltraDMA/33 Mode
DMARDY# Strobe Ideiordy
IOCS0#/IOCS1#
Universal Serial Bus
Sub-ISA Bus Interface
Docw
Fast-PCICLK
Sub-ISA Support of Delayed PCI Transactions
Sub-ISA Bus Cycles
AD310 Read AD310 Write
FRAME# IRDY# TRDY# STOP# Bale ISA RD#, IOR#
5.4 I/O Recovery Delays
REQ# GNT#
Sub-ISA Bus Data Steering
AD310
ISA DMA
SD150
ROM Interface
PCI and Sub-ISA Signal Cycle Multiplexing
Cycle Multiplexed PCI / Sub-ISA Balls
PCI
DMA Controller
FRAME# TRDY#, IRDY#
ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP#
DMA Channels
DMA Transfer Types
DMA Transfer Modes
DMA Controller Registers
DMA Priority
DMA Page Registers and Extended Addressing
Programmable Interval Timer
DMA Addressing Capability
DMA Address Generation
Master
PIC Interrupt Mapping
Programmable Interrupt Controller
Mapping
PIC Shadow Register
PIC Interrupt Sequence
PIC I/O Registers
PCI Compatible Interrupts
7.1 I/O Port 092h System Control
Fast Keyboard Gate Address 20 and CPU Reset
Keyboard Support
7.2 I/O Port 061h System Control
Power Management Logic
Wakeup Events Capability
Power Management Events
Power Planes Control Signals vs Sleep States
Power Planes vs. Sleep/Global States
Thermal Monitoring
Power Button
Power Button Override
AMD Geode SC1200/SC1201 Processor Data Book 161
APM Support
Power Management Programming
CPU Power Management
Suspend Modulation
AMD Geode SC1200/SC1201 Processor Data Book 163
Volt Suspend
Save-to-Disk
General Purpose Timers
Peripheral Power Management
Device Idle Timers and Traps
Acpi Timer Register
F1BAR0+I/O
Power Management SMI Status Reporting Registers
Module
Located at F0 Index xxh Unless Otherwise Noted
Device Power Management Programming Summary
Power Management Programming Summary
F1BAR0+I/O
Gpio Interface
Integrated Audio
Audio Data Buffer Reserved Size
11. Physical Region Descriptor Format
Byte
Memory Region Base Address
PRD1 PRD2
PRD3
12.2 AC97 Codec Interface
Codec Configuration/Control Registers
Codec Command Register
Codec Gpio Status and Control Registers
VSA Technology
Trap SMI Enable Register
VSA Technology Support Hardware
Audio SMI Related Registers
Module Core Logic Module
Internal IRQ Control Register
IRQ Configuration Registers
Internal IRQ Enable Register
LPC Interface
12. Cycle Types
Register Descriptions
PCI Configuration Space and Access Methods
13. PCI Configuration Address Register 0CF8h
Core Logic module. Included in the tables are the regis
Ter’s reset values and page references where the bit for
Register Summary
Mats are found
Width Reset Reference F0 Index Bits
AMD Geode SC1200/SC1201 Processor Data Book 177
32579BCore Logic Module Register Summary
178
F0BAR0+
15. F0BAR0 Gpio Support Registers Summary
16. F0BAR1 LPC Support Registers Summary
F0BAR1+
18. F1BAR0 SMI Status Registers Summary
F1BAR0+
00h-03h Pcnt Processor Control Register
19. F1BAR1 Acpi Support Registers Summary
F1BAR1+
20h PM2CNT PM2 Control Register 00h 21h-FFh Not Used
Width Reset Reference F2 Index Bits
182
22. F3 PCI Header Registers for Audio Support Summary
Width Reset Reference F3 Index Bits
21. F2BAR4 IDE Controller Support Registers Summary
F2BAR4+
F3BAR0+
Width Reset
23. F3BAR0 Audio Support Registers Summary
184
F5BAR0+
Width Reset Reference F5 Index Bits
25. F5BAR0 I/O Control Support Registers Summary
AMD Geode SC1200/SC1201 Processor Data Book 185
Pciusb
26. Pciusb USB PCI Configuration Register Summary
Name Reset Value
Width Reference Index Bits
AMD Geode SC1200/SC1201 Processor Data Book 187
27. Usbbar USB Controller Registers Summary
USBBAR0
188
28. ISA Legacy I/O Register Summary
DMA Page Registers Table
Programmable Interrupt Controller Registers Table
Programmable Interval Timer Registers Table
Port Type Name Reference
Keyboard Controller Registers Table
General Remarks
Chipset Register Space
Bridge, GPIO, and LPC Registers Function
Index 09h-0Bh
Core Logic Module Bridge, GPIO, and LPC Registers Function
Data Parity Detected. This bit is set when
AMD Geode SC1200/SC1201 Processor Data Book 191
Index 0Fh PCI Bist Register RO
Index 0Eh PCI Header Type RO Reset Value 80h
Slave response
316 Gpio Base Address
PCI Subtractive Decode
AMD Geode SC1200/SC1201 Processor Data Book 193
Index 43h
Reset Control Register R/W Reset Value 01h
Index 42h
194
Index 47h
Index 45h
Index 46h
AMD Geode SC1200/SC1201 Processor Data Book 195
PIT Counter 1 Enable
Reset Value 7Bh
PIT Software Reset
PIT Counter 0 Enable
AMD Geode SC1200/SC1201 Processor Data Book 197
ROM/AT Logic Control Register R/W Reset Value 98h
Generate SMI on A20M# Toggle
Index 5Bh Decode Control Register 2 R/W
Bit Description Index 54h-59h
Index 5Ah
198
INTD# Ball AA2 Target Interrupt
INTB# Ball C26 Target Interrupt
INTA# Ball D26 Target Interrupt
INTC# Ball C9 Target Interrupt
200
150
Index 72h
Index 76h
Index 73h
Index 74h-75h
Chip Select 0 Positive Decode IOCS0#
Ing the upper 19 bits of the incoming PCI address AD3113
202
AMD Geode SC1200/SC1201 Processor Data Book 203
Power Management Enable Register 2 R/W Reset Value 00h
Timer expires Disable Enable
204
Parallel/Serial Access Trap
Power Management Enable Register 3 R/W Reset Value 00h
Keyboard/Mouse Access Trap
AMD Geode SC1200/SC1201 Processor Data Book 205
Index 83h Power Management Enable Register 4 R/W
Floppy Disk Access Trap
Primary Hard Disk Access Trap
206
Index 84h Second Level PME/SMI Status Mirror Register 1 RO
AMD Geode SC1200/SC1201 Processor Data Book 207
208
AMD Geode SC1200/SC1201 Processor Data Book 209
210
Index 88h General Purpose Timer 1 Count Register R/W
Reserved. Always reads
AMD Geode SC1200/SC1201 Processor Data Book 211
Re-trigger General Purpose Timer 1 on Floppy Disk Activity
Second Millisecond
212
Index 8Bh General Purpose Timer 2 Control Register R/W
Index 8Dh Video Speedup Timer Count Register R/W
AMD Geode SC1200/SC1201 Processor Data Book 213
Index 8Fh-92h
Index 93h
Index 98h-99h
Index 9Ah-9Bh Floppy Disk Idle Timer Count Register R/W
Index 97h
214
Index A6h-A7h Video Idle Timer Count Register R/W
Index A8h-A9h Video Overflow Count Register R/W
Index B0h-B3h
Index AEh CPU Suspend Command Register WO
Index AFh Suspend Notebook Command Register WO
Index B4h
AMD Geode SC1200/SC1201 Processor Data Book 217
Index B9h PIC Shadow Register RO
Index BAh PIT Shadow Register RO
Index BDh-BFh
Index BCh Clock Stop Control Register R/W Reset Value 00h
Reserved. Set to CPU Clock Stop
Index C0h-C3h
Index CDh
Bit Description Index CCh
Mask
Index CEh
Index F5h Second Level PME/SMI Status Register 2 RC
Index EDh-F3h
Index F4h
220
Index F6h Second Level PME/SMI Status Register 3 RC
AMD Geode SC1200/SC1201 Processor Data Book 221
222
Index F7h Second Level PME/SMI Status Register 4 RC
Reserved. Read as
Index F8h-FFh
Gpio Support Registers
30. F0BAR0+I/O Offset Gpio Configuration Registers
I/O mapped registers accessed through F0BAR0
Ration registers are located. -29gives the bit formats
316 Reserved. Must be set to
Offset 14h-17h GPDI1 Gpio Data In 1 Register RO
F0BAR0+I/O Offset 18h is set, this edge generates a PME
AMD Geode SC1200/SC1201 Processor Data Book 225
010011 = GPIO19 ball C9 000100
Bank
010010 = GPIO18 ball AG1 000011
010100 = GPIO20 balls A9, N31 000101
AMD Geode SC1200/SC1201 Processor Data Book 227
3121
31. F0BAR1+I/O Offset LPC Interface Configuration Registers
LPC Support Registers
Reserved. Set to
AMD Geode SC1200/SC1201 Processor Data Book 229
Polarity selection
230
Number of IRQ Data Frames
Reserved Serial IRQ Enable
Serial IRQ Interface Mode
AMD Geode SC1200/SC1201 Processor Data Book 231
232
LPC Floppy Disk Controller Address Select. Selects I/O Port
LPC Game Port 1 Address Select. Selects I/O Port
LPC Game Port 0 Address Select. Selects I/O Port
LPC Midi Address Select. Selects I/O Port
234
Bit
SMI Status and Acpi Registers Function
32. F1 PCI Header Registers for SMI Status and Acpi Support
Core Logic Module SMI Status and Acpi Registers Function
33. F1BAR0+I/O Offset SMI Status Registers
SMI Status Support Registers
AMD Geode SC1200/SC1201 Processor Data Book 237
238
Suspend Modulation Enable Mirror. Read to Clear
Offset 02h-03h Top Level PME/SMI Status Register RO/RC
AMD Geode SC1200/SC1201 Processor Data Book 239
Offset 04h-05h
Yes To enable SMI generation, set F0 Index 82h6 =
Yes To enable SMI generation, set F0 Index 82h5 =
240
AMD Geode SC1200/SC1201 Processor Data Book 241
242
Offset 0Ah-1Bh
These addresses should not be written Offset 1Ch-1Fh
AMD Geode SC1200/SC1201 Processor Data Book 243
Offset 24h-27h External SMI Register R/W
3124
244
AMD Geode SC1200/SC1201 Processor Data Book 245
246
Offset 28h-4Fh Not Used Reset Value 00h
50h-FFh
Acpi Support Registers
Offset 06h Smicmd OS/BIOS Requests Register R/W
34. F1BAR1+I/O Offset Acpi Support Registers
Clkval Clock Throttling Value. CPU duty cycle
SCI generation is always enabled
248
Offset 0Ch-0Dh PM1ACNT PM1A Control Register R/W
Offset 0Ah-0Bh PM1AEN PM1A PME/SCI Enable Register R/W
1511
1514 Reserved. Must be set to
250
AMD Geode SC1200/SC1201 Processor Data Book 251
252
Consumer Electronic Infrared
Gpwio Control Register 1 R/W Reset Value 00h
Gpwio Control Register 2 R/W Reset Value 00h Reserved
02h0
Gpwio Data Register R/W Reset Value 00h
Reserved Reset Value 00h 254
Offset 21h-FFh
Reset Value 00000F00h
Bit Description Offset 18h-1Bh
AMD Geode SC1200/SC1201 Processor Data Book 255
IDE Controller Registers Function
Bit Description Index 30h-3Fh
PIOMODE. PIO mode
Core Logic Module IDE Controller Registers Function
AMD Geode SC1200/SC1201 Processor Data Book 257
258
Index 58h-5Bh
Bit Description Index 48h-4Bh
Index 50h-53h
Index 60h-FFh
IDE Controller Support Registers
260
Offset 0Bh
Offset 09h
Offset 0Ah
Offset 0Ch-0Fh
37. F3 PCI Header Registers for Audio Configuration
Audio Registers Function
Core Logic Module Audio Registers Function
38. F3BAR0+Memory Offset Audio Configuration Registers
Audio Support Registers
Offset 04h-07h
264
AMD Geode SC1200/SC1201 Processor Data Book 265
266
These bits change only on a fast write to an even address
2316
AMD Geode SC1200/SC1201 Processor Data Book 267
268
Mask Internal IRQ11. Write Only
Mask Internal IRQ15. Write Only
Mask Internal IRQ14. Write Only
Mask Internal IRQ10. Write Only
Assert Masked Internal IRQ14
Mask Internal IRQ4. Write Only
Mask Internal IRQ3. Write Only
Reserved. Set to Assert Masked Internal IRQ12
Bit Description Assert Masked Internal IRQ1
AMD Geode SC1200/SC1201 Processor Data Book 271
Offset 2Ah-2Bh
Audio Bus Master 1 Command Register R/W Reset Value 00h
Offset 29h Audio Bus Master 1 SMI Status Register RC
Offset 2Ch-2Fh
Offset 32h-33h
Audio Bus Master 2 Command Register R/W Reset Value 00h
Offset 31h Audio Bus Master 2 SMI Status Register RC
Offset 34h-37h
Offset 3Ah-3Bh
Audio Bus Master 3 Command Register R/W Reset Value 00h
Offset 39h Audio Bus Master 3 SMI Status Register RC
Offset 3Ch-3Fh
Offset 42h-43h
Audio Bus Master 4 Command Register R/W Reset Value 00h
Offset 41h Audio Bus Master 4 SMI Status Register RC
Offset 44h-47h
Offset 4Ah-4Bh
Audio Bus Master 5 Command Register R/W Reset Value 00h
Offset 49h Audio Bus Master 5 SMI Status Register RC
Offset 4Ch-4Fh
Bus Expansion Interface Function
39. F5 PCI Header Registers for X-Bus Expansion
Index 24h-27h
Bit Description Index 1Ch-1Fh
Index 20h-23h
Index 28h-2Bh
Index 4Ch-4Fh F5BAR3 Mask Address Register R/W
Index 58h F5BARx Initialized Register R/W Reset Value 00h
Index 48h-4Bh F5BAR2 Mask Address Register R/W
Index 50h-53h F5BAR4 Mask Address Register R/W
280
Bit Description Index 64h-67h
Index 68h-FFh
F5 Index 10h, Base Address Register 0 F5BAR0 set
40. F5BAR0+I/O Offset X-Bus Expansion Registers
Bus Expansion Support Registers
Iotestporten Debug Test Port Enable
Three USB transceivers. Default = 128
USB transceivers. Default =
282
Core Logic Module USB Controller Registers Pciusb
41. Pciusb USB PCI Configuration Registers
USB Controller Registers Pciusb
AMD Geode SC1200/SC1201 Processor Data Book 283
Bit Description Index 06h-07h Status Register R/W
Reset Value 08h
Index 0Dh Latency Timer Register R/W
Reserved. Must be set to Index 08h
42. USBBAR+Memory Offset USB Controller Registers
32579BCore Logic Module USB Controller Registers Pciusb
286
RootHubStatusChangeEnable
HcInterruptEnable Register R/W Reset Value = 00000000h
OwnershipChangeEnable
FrameNumberOverflowEnable
Offset 24h-27h
Bit Description StartOfFrameEnable
Offset 20h-23h
Offset 28h-2Bh
Bit Description Offset 38h-3Bh HcFrameRemaining Register RO
Reset Value = 00000628h
Reset Value = 01000003h
Reserved. Read 0s
Offset 50h-53h HcRhStatus Register R/W
BalPower
Read LocalPowerStatusChange. Not supported. Always read
3018
Read PortSuspendStatus
HcRhPortStatus1 Register R/W Reset Value = 00000000h
Read PortResetStatus
AMD Geode SC1200/SC1201 Processor Data Book 291
292
Read PortEnableStatus
Read CurrentConnectStatus
AMD Geode SC1200/SC1201 Processor Data Book 293
Reserved Reset Value = xxh 294
AMD Geode SC1200/SC1201 Processor Data Book 295
ISA Legacy Register Space
43. DMA Channel Control Registers
Core Logic Module ISA Legacy Register Space
Priority Mode
Timing Mode
Write
32579BCore Logic Module ISA Legacy Register Space
Transfer Mode
Channel Number Mode Select
Bit Description Port 00Bh
AMD Geode SC1200/SC1201 Processor Data Book 299
Write DMA Command Register, Channels
Undefined
Port 0D6h
Bit Description Port 0D2h
Port 0D4h
Port 0D8h
44. DMA Page Registers
45. Programmable Interval Timer Registers
Counter Value Read
Current Counter Mode BCD Mode
Bit Description Port 042h Write
Port 043h R/W
46. Programmable Interrupt Controller Registers
Bit Description IRQ1 / IRQ9 Mask
Poll Command
Register Read Mode
IRQ0 / IRQ8 Mask
IRQ5 / IRQ13 In-Service
Interrupt Service Register IRQ7 / IRQ15 In-Service
IRQ6 / IRQ14 In-Service
IRQ4 / IRQ12 In-Service
47. Keyboard Controller Registers
48. Real-Time Clock Registers
49. Miscellaneous Registers
AMD Geode SC1200/SC1201 Processor Data Book 309
310
Hardware Video Acceleration
General Features
Video Input Port VIP Interface
Graphics-Video Overlay and Blending
VIP
Display Modes
Video Input Port
Tvout
VBI Support
Functional Description
Video Support
Video Processor Module
Active Video
Video Input Port VIP
Direct Mode and Capture Mode Configurations
AMD Geode SC1200/SC1201 Processor Data Book 317
Bob
Address not changed during runtime
Weave
AMD Geode SC1200/SC1201 Processor Data Book 319
Capture VBI Mode
Ping-pongs between the two buffers during runtime
Line Buffer
Video Block
Video Input Formatter
320
Horizontal Downscaler
Horizontal Downscaler with 4-Tap Filtering
Filtering
Maintaining Aspect Ratio
2.5 2-Tap Vertical and Horizontal Upscalers
Line Buffers
Formatter
Ai,j Ai,j+1 Ai+1,jAi+1,j+1
RGB
Mixer/Blender Block
CSC
RAM
Flicker
Valid Mixing/Blending Configurations
Filter2 Bit Mode Comment
324
RGB to YUV CSC
YUV to RGB CSC in Video Data Path
Gamma Correction
3.4 1/2 Y Flicker Filter
Cursor Window
Graphics Window
Video Window
Alpha Windows
Color
Truth Table for Alpha Blending
Mixing/Blending Operation
CHROMASEL1
328
Flicker Filter and Scan Rate Conversion
Flicker Filter, Interlaced Video YUV Mixing/Blending Mode
Tvout Block
Vesa
Vesa DDSC2B and Dpms Support
Integrated DACs
HSYNC, VSYNC, TFTDE, Tftdck
Power Sequence
TFT Interface
T1 is a programmable multiple of frame time T0+T1
Compare Pump Filter Divider Out
Divider Phase Charge Loop
Integrated PLL
332
F4BAR0+
F4BAR0 Video Processor Configuration Registers Summary
F4 PCI Header Registers for Video Processor Support Summary
32579BVideo Processor Module Register Summary
334
Encoder Registers
Name Value Tvout Configuration Registers
F4BAR2 VIP Support Registers Summary
F4BAR2+
Video Processor Registers Function
Reset Value 0504h
Reset Value 030000h
3112 VIP Base Address 110 Address Range. Read Only
AMD Geode SC1200/SC1201 Processor Data Book 337
Video Processor Module Video Processor Registers Function
Index 3Eh-FFh Reserved
Video Processor Support Registers F4BAR0
Video Configuration Register R/W Reset Value 00000000h
EN42X Enable 42x Format. Allows format selection
To 0 or 1 should be written with a value that is read
3028
Offset 04h-07h Display Configuration Register R/W
Tions of the power sequence control lines 1614
Ddcsdaout DDC Output Data. DDC data bit for output
Offset 08h-0Bh Video X Position Register R/W
340
Bit Description 100
AMD Geode SC1200/SC1201 Processor Data Book 341
Bit Description Offset 1Ch-1Fh
Reset Value 00001400h
12 PLL2PWREN PLL2 Power-Down Enable
Block Offset 20h-23h
FLTCO4 Filter Coefficient 4. For the tap-4 filter
DTS Downscale Type Select
Offset 40h-43h Video Downscaler Coefficient Register R/W
FLTCO3 Filter Coefficient 3. For the tap-3 filter
Reset Value 00060000h
Reserved Signen Signature Enable
Reset Value 0000xxxxh
Bit Description Offset 44h-47h CRC Signature Register R/W
100 i.e., shift one line otherwise, leave at
AMD Geode SC1200/SC1201 Processor Data Book 345
Offset 60h-63h Alpha Window 1 X Position Register R/W
Bit Description Offset 50h-53h
Offset 54h-57h
346
AMD Geode SC1200/SC1201 Processor Data Book 347
3118
Decremented until it is reloaded via bit 17 Loadalpha
348
Offset 400h-403h
Offset 90h-93h
Offset 94h-97h
Video Fifo Underflow Empty
VBI Fifo Overflow Full
Video Fifo OverFlow Full
VBI Fifo Underflow Empty
Upscale horizontally VBI data by
3120 Reserved 190
Genlocktouten GenLock Timeout Enable
Bit Description Offset 414h-417h
Port Offset 41Ch-41Fh
Offset 424h-427h
Ctgenlocken Enable Continuous GenLock Function
Sggenlocken Enable a Single GenLock Function
3121 Reserved 200
Bit Description Offset 80Ch-80Fh
Offset 810h-813h
Offset 81Ch-81Fh
Horintp Horizontal Interpolation
Fieldinvr Field Invert
Offset C00h-C03h
2920
AMD Geode SC1200/SC1201 Processor Data Book 355
Offset C08h-C0Bh
TV DAC Mode Bits Ball No
A23 Mode
D24 A24
Offset C28h-C2Bh
Offset C24h-C27h
3114
AMD Geode SC1200/SC1201 Processor Data Book 357
Bit Description Offset C2Ch-C2Fh
Reset Value 00000020h
Reset Value 00000004h
Offset C50h-C53h
All other decodes Reserved
10. F4BAR2+Memory Offset VIP Configuration Registers
VIP Support Registers F4BAR2
AMD Geode SC1200/SC1201 Processor Data Book 359
Reserved.Read Only Current Field. Read Only
Capture Store to Memory VBI Data
Capture Store to Memory Video Data
2322
Offset 14h-17h
Video Data Capture Active. Read Only
Reserved. Read Only Run Status. Read Only
Offset 24h-27h Video Data Even Base Register R/W
Offset 44h-47h VBI Data Even Base Register R/W
3116 Reserved 150
Offset 2Ch-3Fh
Offset 48h-4Bh VBI Data Pitch Register R/W
Mandatory Instruction Support
Jtag Mode Instruction Support
Testability Jtag
Optional Instruction Support
364
Electro Static Discharge ESD
General Specifications
Power/Ground Connections and Decoupling
Absolute Maximum Ratings
366
Symbol Parameter Min Typ Max Unit Comments
Operating Conditions
Power State Parameter Definitions
Power Planes of External Interface Signals
Power Plane Signal Names VCC Balls VSS Balls
DC Current
DC Characteristics for On State
Symbol Parameter Min Typ Max Unit Comment
DC Characteristics for Active Idle, Sleep, and Off States
Symbol Parameter Note Min Typ Max Unit Comments
Ball Capacitance and Inductance
VIO
Pull-Up and Pull-Down Resistors
Balls with PU/PD Resistors
External PU or PD resistor
Wire
DC Characteristics
Symbol Description Reference
10. Buffer Types
Inpci DC Characteristics
Inab DC Characteristics
Inbtn DC Characteristics
Ints DC Characteristics
Instrp DC Characteristics
INT DC Characteristics
INTS1 DC Characteristics
Inusb DC Characteristics
ODn DC Characteristics
Opci DC Characteristics
Odpci DC Characteristics
Op/n DC Characteristics
Ousb DC Characteristics
Symbol Parameter Value
AC Characteristics
11. Default Levels for Measurement Switching Parameters
CLK
Inputs
Memory Controller Interface
Outputs
SDCLK30, Sdclkout high time
32579BElectrical Specifications
12. Memory Controller Timing Parameters
13.5
BA10, MD630
T1, t2, t3 t10
SDCLK30 Control Output, MA120
MD630 Data Valid Read Data
Vpckin Vref
14. Video Output Port Timing Parameters
CRT and TFT Interface
15. TFT Timing Parameters
Symbol Parameter Note Min Max Unit Comments
16. CRT Vesa Compatible DAC RED, GREEN, and Blue Outputs
LSB DNL
RES
IRE
LSB Tvref
19. ACCESS.bus Output Timing Parameters
ACCESS.bus Interface
18. ACCESS.bus Input Timing Parameters
AB1D AB2D
AB1C AB2C
AMD Geode SC1200/SC1201 Processor Data Book 387
AB1D AB2D AB1C AB2C
AB1D AB2D AB1C
20. PCI AC Specifications
PCI Bus
64VIO
Equation a Equation B
21. PCI Clock Parameters
Pciclk 0.4 V IO
22. PCI Timing Parameters
Measurement and Test Conditions
Symbol Value Unit Comments
23. Measurement Condition Parameters
Input Valid
Power
Signals
Ms typ
24. Sub-ISA Timing Parameters
Symbol Parameter Bits Type Comments
Sub-ISA Interface
Bus Width Min
Bus Width Min Max Symbol Parameter Bits Type Comments
MEMR#/DOCR#/IOR#
MEMR#/DOCR#
ROMCS#/DOCCS#
IOR#/RD#/TRDE#
IOW#/WR# MEMW#/DOCW#
IOW#/WR# MEMW#/DOCW# TRDE#
DOCCS#/ROMCS#
IOCS10#
D150
LPC Interface 25. LPC and Serirq
IDE Interface Timing 26. IDE General Timing Parameters
IDE signals fall time from 0.9V IO to 0.1V IO = 40 pF
IDE signals rise time from 0.1V IO to 0.9V IO = 40 pF
IDERST# pulse width
Cycle time min
Mode Symbol Parameter Unit Comments
27. IDE Register Transfer to/from Device Timing Parameters
Width 8-bit min
Read IDEDATA70
Addr valid1
IDEIOR0# IDEIOW0# Write IDEDATA70
IDEIORDY0 2,3
402
28. IDE PIO Data Transfer to/from Device Timing Parameters
165 125 100
AMD Geode SC1200/SC1201 Processor Data Book 403
IDEIOR0# IDEIOW0# Write IDEDATA150
Read IDEDATA150
29. IDE Multiword DMA Data Transfer Timing Parameters
AMD Geode SC1200/SC1201 Processor Data Book 405
IDECS10#
IDEDREQ0 IDEDACK0# IDEIOR0# IDEIOW0#
406
Mode Symbol Parameter Min Max Unit Comments
30. IDE UltraDMA Data Burst Timing Parameters
IDEIOR0# HDMARDY0#
IDEREQ0
STOP0
IDEIRDY0 DSTROBE0
IDEDATA150 at host
IDEIRDY0 DSTROBE0 at device
IDEDATA150 at device IDEIRDY0 DSTROBE0 at host
408
IDEIOR0#HDMARDY0#
IDEDREQ0 device IDEDACK0# host
IDEIOW0#STOP0# host
AMD Geode SC1200/SC1201 Processor Data Book 409
410
IDEDREQ0 device
IDEIOW0# STOP0#
IDECS01#
IDEIOW0# STOP0# host IDEIOR0# HDMARDY0# host
IDEIRDY0 DSTROBE0 device IDEDATA150 device
IDEADDR20
IDEIORDY0 DDMARDY0 device
DevicetUI IDEDACK0# host
IDEIOW0# STOP0# host
IDEIOR0# HSTROBE0# host
IDEDATA150 At host IDEIOR0# HSTROBE0# at device
HSTROBE0#
At host
IDEDATA150 at device
IDEIOR0# HSTROBE0#
IDEDREQ0 device IDEDACK0# host IDEIOW0# STOP0# host
IDEIORDY0# DDMARDY0#
414
IDEDACK0# host
IDEIORDY0# DDMARDY0# device
IDEDATA150 host IDEADDR20 IDECS01#
AMD Geode SC1200/SC1201 Processor Data Book 415
416
IDEDREQ0 device IDEDACK0 host IDEIOW0# STOP0# host
IDEDATA150 host IDECS01# IDEADDR20
Low Speed Source Note
Universal Serial Bus USB 31. USB Timing Parameters
Full Speed Receiver EOP Width Note
Receiver data jitter tolerance for paired
Source EOP width
Host upstream
Low Speed Receiver EOP Width Note
Differential Data Lines Crossover Points 2.0
Rise Time Fall Time
Differential Data Lines
Consecutive Transitions
EOP Width
Differential Data to SE0 Skew
Data Crossover Level
Differential Crossover Points Data Lines
SIR signal pulse width
Modulation signal period
TCPN + Transmitter Sharp-IR and Consumer Remote Control
Setting of the Rxhsc bit bit 5 of the Rccfg register
FIR
Fast IR Port Timing 33. Fast IR Port Timing Parameters
MIR
Busy ACK#
STB#
Unit Comments
Symbol Parameter Min
35. Enhanced Parallel Port Timing Parameters
AFD#
36. ECP Forward Mode Timing Parameters
Extended Capabilities Port ECP Timing
Busy
37. ECP Reverse Mode Timing Parameters
BUSY#
Sync inactive to Bitclk startup 162.8 Delay
Audio Interface Timing AC97 38. AC Reset Timing Parameters
AC97RST# inactive to Bitclk 162.8 Startup delay
AC97RST# active low pulse width
40. AC97 Clocks Parameters
AC97CLK Vold
41. AC97 I/O Timing Parameters
SDATAOUT/SYNC SDATAIN, SDATAIN2
42. AC97 Signal Rise and Fall Timing Parameters
Slot
43. AC97 Low Power Mode Timing Parameters
End of Slot 2 to Bitclk Sdatain low
Bitclk Sdataout
44. PWRBTN# Timing Parameters
Power Management
Power management event to ONCTL# Assertion
ONCTL# PWRBTN#
PWRBTN# ONTCL# PWRCNT21 POR#
POR# 32KHZ
434
Jtag Interface 48. Jtag Timing Parameters
TDI, TMS setup time
Non-test inputs setup time
TDI, TMS hold time
TDI TMS TDO
Output Signals
Input Signals
436
Case-to-Ambient Thermal Resistance Example @ 85C
Thermal Characteristics
ΘJC ×C/W
Assume P max = 5W and TA max = 40C Therefore
Heatsink Considerations
Example
Assume P max = 9W and TA max = 40C Therefore
AMD Geode SC1200/SC1201 Processor Data Book 439
Physical Dimensions
Package Specifications
BGU481 Package Bottom View
440
Ordering Part Number Core Frequency
Order Information
Macrovision Product Notice
MHz
Revision # Revisions / Comments
Data Book Revision History
Table A-1. Revision History
Interface
Interface 
GPIO/LPC Bus 
Interface
Measurement
Interface 
