Texas Instruments TMS320DM643x manuals

98 pages596.5 Kb

3Contents
- Preface
9Read This First
- Chapter 1
11Introduction
- www.ti.com
- 121.1 Introduction
- 1.2 Block Diagram
  - Introduction 12 SPRU978E March 2008Submit Documentation Feedback
    - Peripherals
  - Introduction
- Chapter 2
15TMS320C64x+ Megamodule
- 162.1 Introduction
- 2.2 TMS320C64x+ CPU
  - 17TMS320C64x+ CPU
- 182.3 Memory Controllers
- 2.3.1 L1P Controller
  - Memory Controllers
  - 19Figure 2-2. C64x+ Cache Memory Architecture
- 202.3.2 L1D Controller
- 2.3.3 L2 Controller
- 222.4 Internal Peripherals
- 2.4.1 Interrupt Controller (INTC)
- 2.4.2 Power-Down Controller (PDC)
- 232.4.3 Bandwidth Manager
- Chapter 3
25System Memory
- 273.2 Memory Interfaces Overview 3.2.1 DDR2 External Memory Interface
- 3.2.2 External Memory Interface
- Chapter 4
29Device Clocking
- 304.1 Overview
- 4.2 Clock Domains 4.2.1 Core Domains
  - Clock Domains
  - 31Figure 4-1. Overall Clocking Diagram
- 324.2.2 Core Frequency Flexibility
- 334.2.3 DDR2/EMIF Clock
- 344.2.4 I/O Domains
  - Clock Domains
- 354.2.5 Video Processing Back End
- Chapter 5
37PLL Controller
- 385.1 PLL Module
- 5.2 PLL1 Control
- 395.2.1 Device Clock Generation
- 5.2.2 Steps for Changing PLL1/Core Domain Frequency
- 435.3 PLL2 Control
- 5.3.1 Device Clock Generation
- 445.3.2 Steps for Changing PLL2 Frequency
- 485.4 PLL Controller Registers
  - Table 5-4. PLL and Reset Controller Registers
- 495.4.1 Peripheral ID Register (PID)
- 5.4.2 Reset Type Status Register (RSTYPE)
  - Table 5-5. Peripheral ID Register (PID) Field Descriptions
  - Table 5-6. Reset Type Status Register (RSTYPE) Field Descriptions
- 505.4.3 PLL Control Register (PLLCTL)
  - Table 5-7. PLL Control Register (PLLCTL) Field Descriptions
- 515.4.4 PLL Multiplier Control Register (PLLM)
- 5.4.5 PLL Controller Divider 1 Register (PLLDIV1)
  - Table 5-8. PLL Multiplier Control Register (PLLM) Field Descriptions
  - Table 5-9. PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
- 525.4.6 PLL Controller Divider 2 Register (PLLDIV2)
- 5.4.7 PLL Controller Divider 3 Register (PLLDIV3)
  - Table 5-10. PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions
  - Table 5-11. PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions
- 535.4.8 Oscillator Divider 1 Register (OSCDIV1)
  - Table 5-12. Oscillator Divider 1 Register (OSCDIV1) Field Descriptions
- 545.4.9 Bypass Divider Register (BPDIV)
  - Table 5-13. Bypass Divider Register (BPDIV) Field Descriptions
- 555.4.10 PLL Controller Command Register (PLLCMD)
- 5.4.11 PLL Controller Status Register (PLLSTAT)
  - Table 5-14. PLL Controller Command Register (PLLCMD) Field Descriptions
  - Table 5-15. PLL Controller Status Register (PLLSTAT) Field Descriptions
- 565.4.12 PLL Controller Clock Align Control Register (ALNCTL)
  - Table 5-16. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
- 575.4.13 PLLDIV Ratio Change Status Register (DCHANGE)
  - Table 5-17. PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
- 585.4.14 Clock Enable Control Register (CKEN)
  - Table 5-18. Clock Enable Control Register (CKEN) Field Descriptions
- 595.4.15 Clock Status Register (CKSTAT)
  - Table 5-19. Clock Status Register (CKSTAT) Field Descriptions
- 605.4.16 SYSCLK Status Register (SYSTAT)
  - Table 5-20. SYSCLK Status Register (SYSTAT) Field Descriptions
- Chapter 6
61Power and Sleep Controller
- 626.1 Introduction
- 636.2 Power Domain and Module Topology
  - Power Domain and Module Topology
  - Table 6-1. DM643x DMP Default Module Configuration
- 646.3 Power Domain and Module States
- 6.3.1 Power Domain States
- 6.3.2 Module States
- 666.5 IcePick Emulation Support in the PSC
- 6.6 PSC Interrupts 6.6.1 Interrupt Events
- 676.6.2 Interrupt Registers
- 686.6.3 Interrupt Handling
- 6.7 PSC Registers
- 696.7.1 Peripheral Revision and Class Information Register (PID)
- 6.7.2 Interrupt Evaluation Register (INTEVAL)
  - Table 6-6. Peripheral Revision and Class Information Register (PID) Field Descriptions
  - Table 6-7. Interrupt Evaluation Register (INTEVAL) Field Descriptions
- 706.7.3 Module Error Pending Register 1 (MERRPR1)
- 6.7.4 Module Error Clear Register 1 (MERRCR1)
  - Table 6-8. Module Error Pending Register 1 (MERRPR1) Field Descriptions
  - Table 6-9. Module Error Clear Register 1 (MERRCR1) Field Descriptions
- 716.7.5 Power Domain Transition Command Register (PTCMD)
- 6.7.6 Power Domain Transition Status Register (PTSTAT)
  - Table 6-10. Power Domain Transition Command Register (PTCMD) Field Descriptions
  - Table 6-11. Power Domain Transition Status Register (PTSTAT) Field Descriptions
- 726.7.7 Power Domain Status 0 Register (PDSTAT0)
  - Table 6-12. Power Domain Status 0 Register (PDSTAT0) Field Descriptions
- 736.7.8 Power Domain Control 0 Register (PDCTL0)
- 746.7.9 Module Status n Register (MDSTATn)
  - Table 6-14. Module Status nRegister (MDSTAT n) Field Descriptions
- 756.7.10 Module Control n Register (MDCTLn)
  - Table 6-15. Module Control nRegister (MDCTL n) Field Descriptions
- Chapter 7
77Power Management
- 787.1 Overview
- 7.2 PSC and PLLC Overview
- 807.4 DSP Sleep Mode Management
- 7.4.1 DSP Sleep Modes 7.4.2 DSP Module Clock ON/OFF
- 817.5 3.3 V I/O Power Down 7.6 Video DAC Power Down
- Chapter 9
85System Module
- 889.6 Bandwidth Management 9.6.1 Bus Master DMA Priority Control
  - Bandwidth Management
- 899.6.2 EDMA Transfer Controller Configuration 9.7 Boot Control
- Chapter 10
91Reset
- 9310.4 DSP Reset
- 10.4.1 DSP Local Reset 10.4.2 DSP Module Reset
- Appendix A
97Revision History
- 98IMPORTANT NOTICE