Xilinx DS610 manuals
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Module 1: Introduction and Ordering InformationSpartan-3 Generation Configuration User Guide www.xilinx.com/spartan3adsp DS610-1 (v2.0) July 16, 2007Spartan-3 Generation FPGA User Guide Module 2: Functional DescriptionXtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide Module 3: DC and Switching CharacteristicsDS610-3 (v2.0) July 16, 2007 Module 4: Pinout DescriptionsDS610-4 (v2.0) July 16, 2007 Data SheetDS610 July 16, 2007 0 0 Product Specification SPARTAN-3A DSPSpartan-3A and Spartan-3A DSP FPGA Differences FeaturesTable 1: < B L B DS610-1 (v2.0) July 16, 2007 Product Specification 3 Spartan-3A DSP FPGA Family: Introduction and Ordering Information4 Architectural OverviewConfiguration I/O CapabilitiesIntroduction and Ordering Information Spartan-3A DSP Family Architecture 5 Figure 1: Table 2: DSP48A Slice Available User I/Os and Differential (Diff) I/O PairsCS484 CSG484 FG676 FGG676 User Diff User Diff (78) (131) (78) (117) Introduction and Ordering Information 6 Package M arkingSpartan-3A DSP FPGA Package Marking Example Figure 2: Pb-Free PackagingThe 5C and 4I Speed Grade/Temperature Range part combinations may be dual marked as 5C/4I. Ordering InformationStandard PackagingSPARTAN -4 CS484LI Example: XC3SD1800A XC3SD1800A -4 CS484LI G Example: XtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide Spartan-3 Generation FPGA User Guide Spartan-3 Generation Configuration User Guide 9 Functional DescriptionDC Electrical Characteristics 11 DC and Switching Characteristics12 Power Supply Specifications Table 4: Table 7: Table 6: Table 5: General Recommended Operating ConditionsSupply Voltage Thresholds for Power-On Reset Supply Voltage Ramp Rate Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data General Recommended Operating Conditions 13 General DC Characteristics for I/O PinsTable 8: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins I VIN = VCCO VCCAUX = 3.0V to 3.6V 167 346 659 A 14 Quiescent Current RequirementsTable 9: Quiescent Supply Current Characteristics 15 Single-Ended I/O StandardsTable 10: Recommended Operating Conditions for User I/Os Using Single-Ended Standards 16 Table 11: DC Characteristics of User I/Os Using Single-Ended Standards DS610-3 (v2.0) July 16, 2007 www.xilinx.com 17 17 Differential I/O Standards IOSTANDARD Attribute Figure 3: Table 12: Differential Input Voltages Recommended Operating Conditions for User I/Os Using Differential Signal Standards 18 Figure 4: V VOUTP - VOUTN = Output common mode voltage = 218 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Differential Output Voltages Table 13: DC Characteristics of User I/Os Using Differential Signal Standards V V GND level V V Internal Logic V N P VOUTP + VOUTN Differential I/O Pair PinsDS610-3 (v2.0) July 16, 2007 www.xilinx.com 19 External Termination Requirements for Differential I/Ocycles Table 14: CCAUX = 3.3VV External Input Resistors Required for TMDS_33 I/O Standard Figure 7: / th of Bourns Part Number / th of Bourns Part Number CAT16-LV4F12 100 140 External Termination Resistors for BLVDS_25 I/O Standard Figure 6: V CCO = 2.5V / th of Bourns Part Number CAT16-PT4F4 DIFF_TERM=Yes b) Differential pairs using DIFF_TERM=Yes constraint 19 Device DNA Data Retention, Read EnduranceLVDS, RSDS, MINI_LVDS, and PPDS I/O StandardsExternal Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards Figure 5: BLVDS_25 I/O Standard TMDS_33 I/O StandardZ0 = 50100a) Input-only differential pairs or pairs not using DIFF_TERM=Yes constraint DIFF_TERM=No 14 V CCO = 3 . 3 V V CCO = 2.5V V CCO = 3 . 3 V No VCCO Restrictions V CCO = 3 . 3 V V CCO = 2.5V Bank 0 and 2 Any BankZ0 = 50 Z 165 165 VCCO = 2.5V No VCCO Requirement 50 V = 3.3V 3.3V Bank 0 and 2 Device DNA Identifier Memory Characteristics 20 Switching CharacteristicsSoftware Version Requirements 22 I/O TimingTable 17: Pin-to-Pin Clock-to-Output Times for the IOB Output Path 23 Table 18: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous) 24 Table 19: Setup and Hold Times for the IOB Input Path 25 Table 20: Propagation Times for the IOB Input Path 26 Table 21: 27 Table 22: Timing for the IOB Output Path Table 23: Set/Reset Times Timing for the IOB Three-State Path Synchronous Output Enable/Disable Times Asynchronous Output Enable/Disable Times Set/Reset Times 31 Timing Measurement MethodologyFigure 8: Table 25: The capacitive load (CL) is connected between the output and GND. Test Methods for Timing Measurement at I/Os 32 Table 25: 33 Using IBIS Models to Simulate Load Conditions in ApplicationSimultaneously Switching Output Guidelines 36 Configurable Logic Block (CLB) Timing37 Clock Buffer/Multiplexer Switching CharacteristicsTable 29: Table 31: Table 30: CLB Distributed RAM Switching Characteristics CLB Shift Register Switching Characteristics Clock Distribution Switching Characteristics 38 Block RAM Timing39 DSP48A TimingXtremeDSP DSP48A for Spartan-3A DSP FPGA User Guide Table 33: To reference the DSP48A block diagram, see the (UG431). Setup Times for the DSP48A Setup Times of Data/Control Pins to the Input Register Clock Setup Times of Data Pins to the Pipeline Register Clock Setup Times of Data/Control Pins to the Output Register Clock 40 Table 34: Clock to Out, Propagation Delays, and Maximum Frequency for the DSP48AClock to Out from Output Register Clock to Output Pin Clock to Out from Pipeline Register Clock to Output Pins Clock to Out from Input Register Clock to Output Pins Combinatorial Delays from Input Pins to Output Pins Maximum Frequency 41 Digital Clock Manager (DCM) TimingDelay-Locked Loop (DLL)Table 35: 42 Table 36: 42 www.xilinx.com DS610-3 (v2.0) July 16, 2007 Switching Characteristics for the DLL Notes: DS610-3 (v2.0) July 16, 2007 www.xilinx.com 43 43 Digital Frequency Synthesizer (DFS)Symbol Description Table 38: Table 37: Recommended Operating Conditions for the DFSSpeed Grade Units -5 -4 Min Max Min Max Notes: Switching Characteristics for the DFS www.xilinx.com/bvdocs/publications/ s3a_jitter_calc.zip 44 Phase Shifter (PS)Table 39: Table 41: Table 40: Miscellaneous DCM TimingRecommended Operating Conditions for the PS in Variable Phase Mode Switching Characteristics for the PS in Variable Phase Mode Miscellaneous DCM Timing 45 DNA Port TimingTable 42: DNA_PORT Interface Timing 46 Suspend Mode Timingt sw_gts_cycle:512 sw_gts_cycle:1 sw_gwe_cycle:512 sw_gwe_cycle:1 sw_clk:InternalClock suspend_filter:Yes suspend_filter:No Table 43: Figure 9: t t t t Write Protec ted Defined by SUSPEND constraint Entering Suspend Mode Exiting Suspend Modesw_gts_cycle sw_gwe_cycle t Suspend Mode Timing Parameters 47 Configuration and JTAG TimingGeneral Configuration Power-On/Reconfigure Timing(Open-Drain) (Output) Table 44: Figure 10: Waveforms for Power-On and the Beginning of Configuration Power-On Timing and the Beginning of Configuration Bank 2 PROG_B (Input) INIT_B CCLK 48 Configuration Clock (CCLK) CharacteristicsConfigRate(power-on value) Master Mode CCLK Output Period by Table 45: 49 Table 46: ConfigRate Table 48: Table 47: (power-on value) Master Mode CCLK Output Frequency by Option Setting Master Mode CCLK Output Minimum Low and High Time Slave Mode CCLK Input Low and High Time 50 Master Serial and Slave Serial Mode Timing Figure 11: Table 49: Waveforms for Master Serial and Slave Serial Configuration Timing for the Master Serial and Slave Serial Configuration Modes 51 Slave Parallel Mode Timing Figure 12: Table 50: Waveforms for Slave Parallel Configuration Timing for the Slave Parallel Configuration Mode52 www.xilinx.com DS610-3 (v2.0) July 16, 2007 52 Serial Peripheral Interface (SPI) Configuration Timing Figure 13: Table 51: Waveforms for Serial Peripheral Interface (SPI) Configuration Timing for Serial Peripheral Interface (SPI) Configuration ModeSymbol Description Minimum Ma ximum Units TCCLK1 Initial CCLK clock period (see Table 45) T 50 -ns TINITM Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising edge of INIT_B 53 Table 52: Configuration Timing Requirements for Attached SPI Serial Flash --------------------------------- f TVTMCCLn TDCC T TCCS TMCCL TDSU TMCCL TDH TMCCH T54 www.xilinx.com DS610-3 (v2.0) July 16, 2007 54 Byte Peripheral Interface (BPI) Configuration Timing Figure 14: Table 53: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode Symbol Description Minimum Maximum Units TCCLK1 Initial CCLK clock period (see Tabl e 45 ) T 55T 56 IEEE 1149.1/1553 JTAG Test Access Port TimingJTAG Waveforms Table 55: Figure 15: Packaging Pin Types 59 Pinout Descriptions60 Package Pins by TypeTable 56: Table 58: Table 57: 61 Package Thermal Characteristics62 CS484: 484-Ball Chip-Scale Ball Grid ArraySpartan-3A DSP CS484 Pinout . Pinout Table Spartan-3A DSP CS484 Pinout 68 User I/Os by Bank Footprint Migration DifferencesDS610-4 (v2.0) July 16, 2007 www.xilinx.com 69 69 CS484 FootprintBank 2 Bank 3 CS484 Package Footprint (top view) Figure 16: Left Half of Package (top view)I/O: Unrestricted, general-purpose user I/O. 41 INPUT: Unrestricted, general-purpose input pin. 52 DUAL: Configuration, AWAKE pins, then possible VREF: User I/O or input voltage reference for bank. 32 CLK: User I/O, input, or clock buffer input. 3 CONFIG: Dedicated configuration pins, SUSPEND pin. 4 JTAG: Dedicated JTAG port pins. 84 GND: Ground. 24 VCCO: Output voltage supply for bank. 36 VCCINT: Internal core supply voltage (+1.2V). 24 VCCAUX: Auxiliary supply voltage 1234567891011 A B C D F G H N P R T U V Bank 0 70 Right Half of CS484 Package (top view)12 13 14 15 16 17 18 19 20 21 22 Bank 2 Bank 0 71 FG676: 676-Ball Fine-Pitch Ball Grid Arraylist of differences and migration advice, see the "Footprint Migration Differences" section. XC3SD1800A FPGAPinout Table 80 User I/Os by Bank Table 64: DS610-4 (v2.0) July 16, 2007 www.xilinx.com 81 81 FG676 Footprint Bank 2 14 FG676 Package Footprint for XC3SD1800A FPGA (top view) Figure 17: Note: Left Half of Package (top view)I/O: Unrestricted, INPUT: Unrestricted, AWAKE pins, then possible VREF: User I/O or input CLK: User I/O, input, or configuration pins, JTAG: Dedicated JTAG GND: Ground VCCO: Output voltage VCCINT: Internal core VCCAUX: Auxiliary supply voltage. 12345678910111213 A B C E F H J K L N T U Bank 0 Bank 3 82 Right Half of FG676 Package (top view)14 15 16 17 18 19 20 21 22 23 24 25 26 Bank 0 Bank 1 83 XC3SD3400A FPGAPinout TableSpartan-3A DSP FG676 Pinout for XC3SD3400A FPGA 92 User I/Os by Bank Table 66: DS610-4 (v2.0) July 16, 2007 www.xilinx.com 93 93 FG676 Footprint 24 FG676 Package Footprint for XC3SD3400A FPGA (top view) Figure 18: Note: Left Half of Package (top view)I/O: Unrestricted, INPUT: Unrestricted, AWAKE pins, then possible VREF: User I/O or input CLK: User I/O, input, or configuration pins, JTAG: Dedicated JTAG GND: Ground VCCO: Output voltage VCCINT: Internal core VCCAUX: Auxiliary supply voltage. 12345678910111213 A B E F G H J K L N T U Bank 0 Bank 3 94 Right Half of FG676 Package (top view)14 15 16 17 18 19 20 21 22 23 24 25 26 Bank 0 Bank 1 95 Footprint Migration DifferencesTable 67: FG676 Footprint Migration Differences 96 Migration RecommendationsFG676 Footprint Migration Differences Table 67: The following table shows the revision history for this document. 97 SPARTAN-3A DSPwww.xilinx.com/spartan3adsp
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