Xilinx DS610 manual Rt Ω, Differential, Vicm +

DC and Switching Characteristics

Table 25: Test Methods for Timing Measurement at I/Os (Continued)

R

							Inputs and
Signal Standard		Inputs			Outputs		Outputs
(IOSTANDARD)	VREF (V)	VL (V)	VH (V)	RT (Ω)		VT (V)	VM (V)
SSTL3_I	1.5	VREF – 0.75	VREF + 0.75	50		1.5	VREF
SSTL3_II	1.5	VREF – 0.75	VREF + 0.75	25		1.5	VREF
Differential
LVDS_25	-	VICM – 0.125	VICM + 0.125	50		1.2	VICM
LVDS_33	-	VICM – 0.125	VICM + 0.125	50		1.2	VICM
BLVDS_25	-	VICM – 0.125	VICM + 0.125	1M		0	VICM
MINI_LVDS_25	-	VICM – 0.125	VICM + 0.125	50		1.2	VICM
MINI_LVDS_33	-	VICM – 0.125	VICM + 0.125	50		1.2	VICM
LVPECL_25	-	VICM – 0.3	VICM + 0.3	N/A		N/A	VICM
LVPECL_33	-	VICM – 0.3	VICM + 0.3	N/A		N/A	VICM
RSDS_25	-	VICM – 0.1	VICM + 0.1	50		1.2	VICM
RSDS_33	-	VICM – 0.1	VICM + 0.1	50		1.2	VICM
TMDS_33	-	VICM – 0.1	VICM + 0.1	50		3.3	VICM
PPDS_25	-	VICM – 0.1	VICM + 0.1	50		0.8	VICM
PPDS_33	-	VICM – 0.1	VICM + 0.1	50		0.8	VICM
DIFF_HSTL_I_18	0.9	VREF – 0.5	VREF + 0.5	50		0.9	VREF
DIFF_HSTL_II_18	0.9	VREF – 0.5	VREF + 0.5	50		0.9	VREF
DIFF_HSTL_III_18	1.1	VREF – 0.5	VREF + 0.5	50		1.8	VREF
DIFF_HSTL_I	0.9	VREF – 0.5	VREF + 0.5	50		0.9	VREF
DIFF_HSTL_III	0.9	VREF – 0.5	VREF + 0.5	50		0.9	VREF
DIFF_SSTL18_I	0.9	VREF – 0.5	VREF + 0.5	50		0.9	VREF
DIFF_SSTL18_II	0.9	VREF – 0.5	VREF + 0.5	50		0.9	VREF
DIFF_SSTL2_I	1.25	VREF – 0.5	VREF + 0.5	50		1.25	VREF
DIFF_SSTL2_II	1.25	VREF – 0.5	VREF + 0.5	50		1.25	VREF
DIFF_SSTL3_I	1.5	VREF – 0.5	VREF + 0.5	50		1.5	VREF
DIFF_SSTL3_II	1.5	VREF – 0.5	VREF + 0.5	50		1.5	VREF

Notes:

1.Descriptions of the relevant symbols are as follows:

VREF – The reference voltage for setting the input switching threshold VICM – The common mode input voltage

VM – Voltage of measurement point on signal transition VL – Low-level test voltage at Input pin

VH – High-level test voltage at Input pin

RT – Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is required VT – Termination voltage

2.The load capacitance (CL) at the Output pin is 0 pF for all signal standards.

3.According to the PCI specification.

The capacitive load (CL) is connected between the output and GND. The Output timing for all standards, as published in the speed files and the data sheet, is always based on a CL value of zero. High-impedance probes (less than 1 pF) are used for all measurements. Any delay that the test fixture might contribute to test measurements is subtracted

from those measurements to produce the final timing numbers as published in the speed files and data sheet.

32	www.xilinx.com	DS610-3 (v2.0) July 16, 2007
		Product Specification