Xilinx DS610 manual CS484 Footprint, Left Half of Package top view

R

CS484 Footprint

Left Half of Package (top view)

I/O: Unrestricted,

156 general-purpose user I/O.

INPUT: Unrestricted,

41 general-purpose input pin.

DUAL: Configuration,

52AWAKE pins, then possible user I/O.

VREF: User I/O or input

28 voltage reference for bank.

CLK: User I/O, input, or

32clock buffer input.

CONFIG: Dedicated

3configuration pins, SUSPEND pin.

JTAG: Dedicated JTAG

4port pins.

GND: Ground.

84

VCCO: Output voltage

24 supply for bank.

VCCINT: Internal core

36supply voltage (+1.2V).

VCCAUX: Auxiliary supply

24 voltage

Pinout Descriptions

Bank 0

1

2

3

4

5

6

7

8

9

10

11

A

GND

PROG_

I/O

I/O

I/O

I/O

I/O

I/O

I/O

INPUT

I/O

L24N_0 L20P_0

L18P_0

B

L30N_0

L28N_0

L25N_0

L25P_0

L15N_0

VREF_0

GCLK10

GCLK6

B

TMS

VCCAUX

I/O

I/O

VCCO_0

I/O

GND

I/O

I/O

VCCO_0

I/O

L20N_0

L18N_0

L30P_0

L28P_0

L24P_0

L15P_0

GCLK11

GCLK7

C

I/O

I/O

GND

I/O

INPUT

I/O

I/O

I/O

I/O

INPUT

INPUT

0

L02N_3

L02P_3

L29N_0

L21P_0

L26P_0

L22P_0

L16P_0

VREF_0

D

INPUT

TDI

INPUT

INPUT

I/O

I/O

I/O

GND

I/O

I/O

GND

L04P_3

L08P_3

L08N_3

L29P_0

L21N_0

L26N_0

L22N_0

L16N_0

E

INPUT

VCCO_3

I/O

I/O

VCCAUX

INPUT

I/O

I/O

VCCO_0

INPUT

I/O

L04N_3

L31P_0

L19N_0

L09P_3

L09N_3

L27N_0

VREF_3

VREF_0

GCLK9

F

I/O

I/O

I/O

I/O

I/O

GND

I/O

I/O

I/O

I/O

I/O

L31N_0

L19P_0 L17N_0

L06N_3

L06P_3

L01P_3

L03P_3

L03N_3

L27P_0

L23N_0

PUDC_B

GCLK8

GCLK5

G

I/O

GND

I/O

GND

I/O

I/O

VCCINT

I/O

GND

VCCAUX

GND

L11P_3

L01N_3

L07P_3

L07N_3

L23P_0

H

I/O

I/O

I/O

I/O

I/O

I/O

GND

GND

VCCINT

GND

VCCINT

L11N_3

L14P_3

L05P_3

L05N_3

L10P_3

L10N_3

J

I/O

VCCO_3

INPUT

INPUT

VCCO_3

INPUT

INPUT

VCCINT

GND

VCCINT

GND

L14N_3

L12N_3

L16P_3

L16N_3

L12P_3

VREF_3

VREF_3

K

I/O

I/O

I/O

I/O

I/O

I/O

VCCAUX

GND

VCCINT

GND

VCCINT

L19P_3

L17P_3

L17N_3

L13P_3

L13N_3

L15P_3

LHCLK2

I/O

I/O

I/O

I/O

3

L

L19N_3

GND

VCCAUX

GND

VCCINT

GND

VCCINT

GND

L20P_3

L18P_3

Bank

IRDY2

LHCLK4

L15N_3

LHCLK0

LHCLK3

I/O

I/O

I/O

INPUT

I/O

M

GND

L21P_3

VCCAUX

GND

VCCINT

GND

VCCINT

L22P_3

L20N_3

L18N_3

VREF_3

LHCLK5

L23P_3

LHCLK1

TRDY2

LHCLK6

N

I/O

VCCO_3

INPUT

INPUT

I/O

I/O

I/O

VCCINT

GND

VCCINT

GND

L21N_3

L22N_3

L31P_3 L23N_3

L24N_3

L24P_3

LHCLK7

P

I/O

I/O

INPUT

I/O

VCCO_3

I/O

VCCAUX

GND

VCCINT

GND

VCCINT

L32P_3

L25P_3

L25N_3

L31N_3

L26P_3

VREF_3

R

I/O

I/O

I/O

GND

I/O

I/O

GND

VCCINT

GND

VCCINT

GND

L28N_3

L28P_3

L34P_3

L32N_3

L26N_3

T

I/O

GND

INPUT

I/O

I/O

I/O

VCCINT

GND

VCCAUX

GND

VCCAUX

L30P_3

L27P_3

L34N_3

L29N_3

L29P_3

U	I/O	I/O	INPUT	I/O	I/O	GND	I/O	I/O	I/O	I/O	GND
							L02N_2			L14N_2
	L30N_3	L33P_3	L27N_3	L38P_3	L38N_3			L11N_2	L10N_2
							CSO_B			D4
V	I/O	VCCO_3	I/O	I/O	VCCAUX	I/O	I/O	I/O	VCCO_2	I/O	I/O
						L02P_2					L14P_2
	L33N_3		L36N_3	L36P_3			L11P_2	L06N_2		L10P_2
						M2					D5
W	I/O	I/O	I/O	INPUT	I/O	I/O	GND	I/O	INPUT	INPUT	VCCAUX
				2		L07N_2			2
	L35N_3	L37N_3	L37P_3		L03P_2			L06P_2
				VREF_2		VS2			VREF_2
Y	I/O	INPUT	GND	I/O	I/O	INPUT	INPUT	I/O	I/O	I/O	I/O
					L07P_2					L15N_2	L15P_2
	L35P_3	L39P_3		L03N_2				L13P_2	L13N_2
					RDWR_B					GCLK13	GCLK12
A	INPUT	VCCAUX	I/O	I/O	VCCO_2	INPUT	GND	I/O	VCCO_2	I/O	GND
A	L39N_3		L01P_2	L04N_2				L08N_2		L12N_2
	VREF_3		M1							D6
A	GND	INPUT	I/O	I/O	I/O	I/O	I/O	I/O	I/O	I/O	INPUT
B		2	L01N_2	L04P_2	L05P_2	L05N_2	L08P_2	L09P_2	L09N_2	L12P_2	2
		VREF_2	M0					VS1	VS0	D7	VREF_2

Bank 2

Figure 16: CS484 Package Footprint (top view)

DS610-4 (v2.0) July 16, 2007 www.xilinx.com 69

Product Specification