Xilinx DS610 Speed Grade, Symbol Description Conditions, Device Min Units Setup Times, LVCMOS252

DC and Switching Characteristics

R

Table 19: Setup and Hold Times for the IOB Input Path

					Speed Grade
			IFD_DELAY_		-5	-4
Symbol	Description	Conditions	VALUE	Device	Min	Min	Units
Setup Times
TIOPICK	Time from the setup of data at	LVCMOS25(2)	0	All	1.36	1.74	ns
	the Input pin to the active
	transition at the ICLK input of
	the Input Flip-Flop (IFF). No
	Input Delay is programmed.
TIOPICKD	Time from the setup of data at	LVCMOS25(2)	1	All	1.79	2.17	ns
	the Input pin to the active
			2	All	2.55	2.92	ns
	transition at the ICLK input of
	the Input Flip-Flop (IFF). The
			3	All	3.38	3.76	ns
	Input Delay is programmed.
			4	All	3.75	4.32	ns
			5	All	3.81	4.19	ns
			6	All	4.39	5.09	ns
			7	All	5.16	5.98	ns
			8	All	5.69	6.57	ns
Hold Times
TIOICKP	Time from the active transition	LVCMOS25(2)	0	All	-0.71	-0.71	ns
	at the ICLK input of the Input
	Flip-Flop (IFF) to the point
	where data must be held at the
	Input pin. No Input Delay is
	programmed.
TIOICKPD	Time from the active transition	LVCMOS25(2)	1	All	-1.60	-1.60	ns
	at the ICLK input of the Input
			2	All	-2.06	-2.06	ns
	Flip-Flop (IFF) to the point
	where data must be held at the
			3	All	-2.46	-2.46	ns
	Input pin. The Input Delay is
	programmed.		4	All	-2.86	-2.86	ns
			5	All	-2.88	-2.88	ns
			6	All	-3.24	-3.24	ns
			7	All	-3.55	-3.55	ns
			8	All	-3.89	-3.89	ns
Set/Reset Pulse Width

TRPW_IOB Minimum pulse width to SR control input on IOB

Notes:

All

1.33

1.61

ns

1.The numbers in this table are tested using the methodology presented in Table 25 and are based on the operating conditions set forth in Table 7 and Table 10.

2.This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the appropriate Input adjustment from Table 21.

3.These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract the appropriate Input adjustment from Table 21. When the hold time is negative, it is possible to change the data before the clock’s active edge.

24	www.xilinx.com	DS610-3 (v2.0) July 16, 2007
		Product Specification