Xilinx DS610 manual Suspend Mode Timing, Entering Suspend Mode Exiting Suspend Mode

DC and Switching Characteristics

R

Suspend Mode Timing

Entering Suspend Mode

Exiting Suspend Mode

sw_gwe_cycle

sw_gts_cycle

SUSPEND Input

tSUSPENDHIGH_AWAKE

tSUSPENDLOW

AKE

_AW

AWAKE Output

tSUSPEND_GWE

tAWAKE_GWE

Flip-Flops, Block RAM,

Write Protected

Distributed RAM

tAW

tSUSPEND_GTS

_GTS

AKE

FPGA Outputs

Defined by SUSPEND constraint

tSUSPEND_DISABLE

tSUS

PEND_ENABLE

FPGA Inputs,

Blocked

Interconnect

DS610-3_08_061207

Figure 9: Suspend Mode Timing

Table 43: Suspend Mode Timing Parameters

Symbol

Description

Min

Typ

Max

Units

Entering Suspend Mode

TSUSPENDHIGH_AWAKE

Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter

–

7

–

ns

(suspend_filter:No)

TSUSPENDFILTER

Adjustment to SUSPEND pin rising edge parameters when glitch filter

+160

+300

+600

ns

enabled (suspend_filter:Yes)

TSUSPEND_GWE

Rising edge of SUSPEND pin until FPGA output pins drive their defined

–

10

–

ns

SUSPEND constraint behavior

TSUSPEND_GTS

Rising edge of SUSPEND pin to write-protect lock on all writable clocked

–

<5

–

ns

elements

TSUSPEND_DISABLE

Rising edge of the SUSPEND pin to FPGA input pins and interconnect

–

340

–

ns

disabled

Exiting Suspend Mode

TSUSPENDLOW_AWAKE

Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not

–

4 to 108

–

μs

include DCM lock time.

TSUSPEND_ENABLE

Falling edge of the SUSPEND pin to FPGA input pins and interconnect

–

3.7 to 109

–

μs

re-enabled

TAWAKE_GWE1

Rising edge of the AWAKE pin until write-protect lock released on all writable

–

67

–

ns

clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.

TAWAKE_GWE512

Rising edge of the AWAKE pin until write-protect lock released on all writable

–

14

–

μs

clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.

TAWAKE_GTS1

Rising edge of the AWAKE pin until outputs return to the behavior described

–

57

–

ns

in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.

TAWAKE_GTS512

Rising edge of the AWAKE pin until outputs return to the behavior described

–

14

–

μs

in the FPGA application, using sw_clk:InternalClock and

sw_gts_cycle:512.

Notes:

1.These parameters based on characterization.

2.For information on using the Spartan-3A DSP Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs.

46	www.xilinx.com	DS610-3 (v2.0) July 16, 2007
		Product Specification