R

DC and Switching Characteristics

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Timing parameters and their representative values are selected for inclusion below either because they are important as general design requirements or they indicate fundamental device performance characteristics. The Spartan-3A DSP FPGA speed files (v1.29), part of the Xilinx Development Software, are the original source for many but not all of the values. The speed grade designations for these files are shown in Table 15. For more complete, more precise, and worst-case data, use the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist.

Table 15: Spartan-3A DSP v1.29 Speed Grade Designations

Device

Preview

Advance

Preliminary

Production

XC3SD1800A

 

 

 

-4, -5

 

 

 

 

 

XC3SD3400A

 

 

 

-4, -5

 

 

 

 

 

Table 16 provides the recent history of the Spartan-3A DSP

FPGA speed files.

Table 16: Spartan-3A DSP Speed File Version History

 

ISE

 

Version

Release

Description

1.29

ISE 9.2.01i

Production Speed Files for -4 and -5

 

 

speed grades

1.28

ISE 9.2i

Minor updates

 

 

 

1.27

ISE 9.1.03i

Advance Speed Files for -4 speed

grade

 

 

 

DS610-3 (v2.0) July 16, 2007

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Product Specification

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Xilinx DS610 manual Sign Up for Alerts on Xilinx MySupport, Spartan-3A DSP Speed File Version History