Xilinx DS610 manual Pin Types, Types of Pins on Spartan-3A DSP FPGAs

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Spartan-3A DSP FPGA Family: Pinout Descriptions

DS610-4 (v2.0) July 16, 2007 Product Specification

Introduction

This section describes how the various pins on a Spartan™-3A DSP FPGA connect within the supported component packages and provides device-specific thermal characteristics. For general information on the pin functions and the package characteristics, see the Packaging section in:

•UG331: Spartan-3 Generation FPGA User Guide http://www.xilinx.com/bvdocs/userguides/ug331.pdf

Spartan-3A DSP FPGAs are available in both standard and Pb-free, RoHS versions of each package, with the Pb-free version adding a “G” to the middle of the package code.

Table 56: Types of Pins on Spartan-3A DSP FPGAs

Except for the thermal characteristics, all information for the standard package applies equally to the Pb-free package.

Pin Types

Most pins on a Spartan-3A DSP FPGA are general-purpose, user-defined I/O pins. There are, however, up to 12 different functional types of pins on Spartan-3A DSP packages, as outlined in Table 56. In the package footprint drawings that follow, the individual pins are color-coded according to pin type as in the table.

Type/Color	Description	Pin Name(s) in Type
Code
I/O	Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form	IO_#
	differential I/Os.	IO_Lxxy_#
INPUT	Unrestricted, general-purpose input-only pin. This pin does not have an output structure	IP_#
	or PCI clamp diode.	IP_Lxxy_#
	Dual-purpose pin used in some configuration modes during the configuration process and	M[2:0]
	then usually available as a user I/O after configuration. If the pin is not used during	PUDC_B
	configuration, this pin behaves as an I/O-type pin. See UG332: Spartan-3 Generation	CCLK
	Configuration User Guide for additional information on these signals.	MOSI/CSI_B
		D[7:1]
		D0/DIN
DUAL		CSO_B
		RDWR_B
		INIT_B
		A[25:0]
		VS[2:0]
		LDC[2:0]
		HDC
	Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other	IP/VREF_#
VREF	VREF pins in the same bank, provides a reference voltage input for certain I/O standards.	IP_Lxxy_#/VREF_#
	If used for a reference voltage within a bank, all VREF pins within the bank must be	IO/VREF_#
	connected.	IO_Lxxy_#/VREF_#
	Either a user-I/O pin or an input to a specific clock buffer driver. Packages have 16 global	IO_Lxxy_#/GCLK[15:0],
CLK	clock inputs that optionally clock the entire device. The RHCLK inputs optionally clock the	IO_Lxxy_#/LHCLK[7:0],
	right half of the device. The LHCLK inputs optionally clock the left half of the device. See	IO_Lxxy_#/RHCLK[7:0]
	the Using Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User
	Guide for additional information on these signals.
	Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every	DONE, PROG_B
CONFIG	package has two dedicated configuration pins. These pins are powered by VCCAUX. See
	the UG332: Spartan-3 Generation Configuration User Guide for additional information on
	the DONE and PROG_B signals.
PWR	Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated	SUSPEND, AWAKE
	pin. AWAKE is a Dual-Purpose pin. Unless Suspend mode is enabled in the application,
MGMT
	AWAKE is available as a user-I/O pin.
JTAG	Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has	TDI, TMS, TCK, TDO
	four dedicated JTAG pins. These pins are powered by VCCAUX.

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Product Specification