Slave Parallel Mode Timing | Xilinx DS610 instruction

R

DC and Switching Characteristics

Slave Parallel Mode Timing

PROG_B
(Input)
INIT_B
(Open-Drain)
	TSMCSCC		T	SMCCCS
				SMCCCS
CSI_B
(Input)	TSMCCW
	TSMCCW			TSMWCC
				TSMWCC
RDWR_B
(Input)		TMCCH
		TMCCH	TMCCL
		TSCCH	TSCCL
CCLK
(Input)			1/FCCPAR
	TSMDCC	TSMCCD	1/FCCPAR
D0 - D7	Byte 0	Byte 1	Byte n Byte n+1
	Byte 0	Byte 1	Byte n Byte n+1

(Inputs)

DS529-3_02_051607

Notes:

1.It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B switches High, be careful to avoid contention on the D0 - D7 bus.

Figure 12: Waveforms for Slave Parallel Configuration

Table 50: Timing for the Slave Parallel Configuration Mode

			All Speed Grades

Symbol		Description	Min	Max	Units
Setup Times

TSMDCC(2)	The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin		7	-	ns
TSMCSCC	Setup time on the CSI_B pin before the rising transition at the CCLK pin		7	-	ns
TSMCCW	Setup time on the RDWR_B pin before the rising transition at the CCLK pin		17	-	ns
Hold Times

TSMCCD	The time from the rising transition at the CCLK pin to the point when data is last held at		1	-	ns
	the D0-D7 pins
TSMCCCS	The time from the rising transition at the CCLK pin to the point when a logic level is last		0	-	ns
	held at the CSO_B pin
TSMWCC	The time from the rising transition at the CCLK pin to the point when a logic level is last		0	-	ns
	held at the RDWR_B pin
Clock Timing

TCCH	The High pulse width at the CCLK input pin		5	-	ns
TCCL	The Low pulse width at the CCLK input pin		5	-	ns
FCCPAR	Frequency of the clock signal	No bitstream compression	0	80	MHz
	at the CCLK input pin
	at the CCLK input pin	With bitstream compression	0	80	MHz
		With bitstream compression	0	80	MHz

Notes:

1.The numbers in this table are based on the operating conditions set forth in Table 7.

2.Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.

DS610-3 (v2.0) July 16, 2007

www.xilinx.com

51

Product Specification

Image 51

Xilinx DS610 manual Slave Parallel Mode Timing

Contents

DS610-3 v2.0 July 16 Product SpecificationDS610-1 v2.0 July 16 DS610-2 v2.0 July 16 Data Sheet Features IntroductionSpartan-3A and Spartan-3A DSP Fpga Differences Introduction and Ordering Information ConfigurationArchitectural Overview Capabilities XC3SD3400A DCMCS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A 519 227 Pb-Free Packaging Package MarkingOrdering Information Standard Packaging Date Version Revision Revision History Introduction and Ordering Information DS610-2 v2.0 July 16 Added Low-power options no changes to this module Functional Description Absolute Maximum Ratings DC Electrical CharacteristicsSymbol Description Conditions Min Max Units Absolute Maximum Ratings Symbol Description Min Max Units Power Supply SpecificationsDC and Switching Characteristics Supply Voltage Thresholds for Power-On Reset General DC Characteristics for I/O Pins Symbol Description Test Conditions Min Typ Max Units= GND Maximum2 Quiescent Supply Current CharacteristicsTypical2 Commercial Industrial Symbol Description Device Quiescent Current Requirements Single-Ended I/O Standards CCO for DriversAttribute Min Nom Max Attribute Max Min Test Logic Level Conditions CharacteristicsAttribute Test Logic Level Conditions Differential I/O Standards Iostandard Attribute CCO for DriversMin Nom Max Min mV Nom mV Max mV Iostandard Attribute Min mV Typ mV Max mV External Termination Requirements for Differential I/O Device DNA Identifier Memory CharacteristicsSymbol Description Minimum Units Device DNA Data Retention, Read Endurance Software Version Requirements Switching Characteristics Sign Up for Alerts on Xilinx MySupport Spartan-3A DSP Speed File Version HistorySpartan-3A DSP v1.29 Speed Grade Designations At the Output pin. The DCM is not Use TimingPin-to-Pin Clock-to-Output Times for the IOB Output Path Rate, without DCM Hold Times Ifddelayvalue = Speed Grade Symbol Description ConditionsDevice Min Units Setup Times Set/Reset Pulse Width Ioplid Differential Standards Single-Ended StandardsLvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI333 PCI663 Set/Reset Times Asynchronous Output Enable/Disable TimesTiming for the IOB Three-State Path QuietIO QuietIO 27.67 QuietIO 24.97 QuietIO 25.92 Inputs Only LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25 Inputs Signal Standard Inputs OutputsTiming Measurement Methodology Test Methods for Timing Measurement at I/Os RT Ω DifferentialVicm + Simultaneously Switching Output Guidelines Equivalent VCCO/GND Pairs per BankDevice CS484 FG676 XC3SD1800A XC3SD3400A Signal Standard Top, Bottom Left, Right Package TypeCS484, FG676 Differential Standards Number of I/O Pairs or Channels QuietIO PCI333 PCI663 Configurable Logic Block CLB Timing CLB Slicem TimingClock Timing Clock Buffer/Multiplexer Switching Characteristics CLB Shift Register Switching CharacteristicsClock Distribution Switching Characteristics Block RAM Timing Block RAM TimingClock Frequency DSP48A Timing Setup Times for the DSP48ASpeed Grade Symbol Description Setup Times of Data Pins to the Pipeline Register Clock Maximum Frequency Clock to Out from Pipeline Register Clock to Output PinsClock to Out from Input Register Clock to Output Pins Combinatorial Delays from Input Pins to Output Pins Recommended Operating Conditions for the DLL Delay-Locked Loop DLLInput Clock Jitter Tolerance Delay Path Variation4 Digital Clock Manager DCM Timing Speed Grade Symbol Description Recommended Operating Conditions for the DFS Switching Characteristics for the DFSSpeed Grade Symbol Description Units Min Max Digital Frequency Synthesizer DFS Miscellaneous DCM Timing Phase Shifter PSSwitching Characteristics for the PS in Variable Phase Mode Phase Shifting Range Dnaport Interface Timing DNA Port Timing Symbol Description Min Typ Max Units Suspend Mode TimingEntering Suspend Mode Exiting Suspend Mode Entering Suspend Mode Configuration and Jtag Timing General Configuration Power-On/Reconfigure TimingAll Speed Grades Symbol Description Device Min Max Units 11.2 Configuration Clock Cclk CharacteristicsMaster Mode Cclk Output Period by ConfigRate Option Setting Cclk clock period by Cclk Low and High time Master Mode Cclk Output Minimum Low and High TimeSlave Mode Cclk Input Low and High Time Equivalent Cclk clock frequency Master Serial and Slave Serial Mode Timing Slave All Speed Grades Symbol DescriptionMin Max Units Clock-to-Output Times Slave Parallel Mode Timing Symbol Description Minimum Serial Peripheral Interface SPI Configuration Timing Symbol Description Requirement Units Hold time on M20 mode pins after the rising edge of Initb Byte Peripheral Interface BPI Configuration TimingSymbol Description Minimum Maximum Units Setup time on M20 mode pins before the rising edge of Initb Parallel NOR Flash Prom chip-select time Symbol Description Requirement UnitsParallel NOR Flash Prom output-enable time Parallel NOR Flash Prom read access time INTEST, EXTEST, Sample Ieee 1149.1/1553 Jtag Test Access Port Timing DSP48A timing in and Table Diffhstli and Diffhstliii to , , and . Updated Tmds DC DC and Switching Characteristics Types of Pins on Spartan-3A DSP FPGAs Pin TypesType/Color Description Pin Names in Type Code Maximum User I/O by Package Package Pins by TypePinout Descriptions Types of Pins on Spartan-3A DSP FPGAs Power and Ground Supply Pins by Package Package Thermal Characteristics Spartan-3A DSP Package Thermal CharacteristicsPinout Descriptions Bank Pin Name CS484 Type Ball CS484 484-Ball Chip-Scale Ball Grid ArrayPinout Table Spartan-3A DSP CS484 Pinout Pinout Descriptions Spartan-3A DSP CS484 Pinout AA6 Input VCCO1AA3 Dual AA4 AA1 Vref VCCO2 AA5 Vcco AA9VCCO2 VCCO2 Vcco VCCO3 Vcco GND AA7GND AB1 Vccaux TMS Jtag TDO Vccaux Progb Config DoneVccaux TCK Jtag User I/Os Per Bank for the XC3SD3400A in the CS484 Package User I/Os by BankFootprint Migration Differences User I/Os Per Bank for the XC3SD1800A in the CS484 Package Left Half of Package top view CS484 Footprint Right Half of CS484 Package top view Spartan-3A DSP FG676 Pinout for XC3SD1800A Fpga FG676 676-Ball Fine-Pitch Ball Grid ArrayPinout Table Spartan-3A DSP FG676 Pinout for IOL26N0/GCLK7 IOL26P0/GCLK6 IOL31P1/RHCLK2 IOL30N1/RHCLK1IOL30P1/RHCLK0 IOL33P1/RHCLK4 IOL27P2/GCLK0 IOL17P2/RDWRB AF7 Input AF3AF4 AF5 IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 Vref IP2/VREF2 AB6 VrefAB9 IOL30N2/MOSI/CSIB IOL35N3/LHCLK7 IOL33P3/LHCLK2IOL34N3/LHCLK5 IOL34P3/LHCLK4 AD2 AE1 InputAE2 Vref AD1 GND AA1 AA6 Vccaux Progb Config TDI Jtag TDOGND AF1 AF6 GND AD3 AD8 519 314 User I/Os by BankUser I/Os Per Bank for the XC3SD1800A in the FG676 Package Top 128 Right FG676 Package Footprint for XC3SD1800A Fpga top view FG676 Footprint TDO IOL01P0 G20 Spartan-3A DSP FG676 Pinout for XC3SD3400A FpgaBank XC3SD3400A Pin Name FG676 Type Ball IOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0 IP1/VREF1 VCCO0 Vcco IOL01P1/HDC IOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16 IOL34P1/IRDY1/RHCLK6 IOL05N1 AC25 IOL06P1 T25IOL12P2 Y10 VCCO2 AF7 Vcco AE5 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17 IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22 IOL53P3 IOL53N3 IP3 IOL36N3 IOL37P3IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IP3/VREF3 Vref IOL10N3 IOL03N3 IP3AA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND GND AA1 AA4 AA6 GND AD3 AD5 AD8GND AC5 AC7 GND AB3 Vccint AA8 Vccaux AF2 AB4 AB5 Bottom 112 Left Vref are on Input pinsUser I/Os Per Bank for the XC3SD3400A in the FG676 Package Top 111 Right Pinout Descriptions FG676 Package Footprint for XC3SD3400A Fpga top view VCCO0 VREF1 VREF1 FG676 Footprint Migration Differences Pinout Descriptions FG676 Footprint Migration Differences Migration Recommendations Fpga and XC3SD3400A Fpga . Minor edits SPARTAN-3A DSP Pinout Descriptions