Main
Module 1: Introduction and Ordering Information
Spartan-3 Generation Configuration User Guide
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Data Sheet
DS610 July 16, 2007 0 0 Product Specification
SPARTAN-3A DSP
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Spartan-3A and Spartan-3A DSP FPGA Differences
Features
Table 1:
< B L B
Spartan-3A DSP FPGA Family: Introduction and Ordering Information
Architectural Overview
Configuration
I/O Capabilities
Introduction and Ordering Information
DCM
Figure 1:
CLBs
Table 2:
DSP48A Slice
Available User I/Os and Differential (Diff) I/O Pairs
Package M arking
Spartan-3A DSP FPGA Package Marking Example
Figure 2:
Pb-Free Packaging
The 5C and 4I Speed Grade/Temperature Range part combinations may be dual marked as 5C/4I.
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XtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide
Spartan-3 Generation FPGA User Guide
Spartan-3 Generation Configuration User Guide
Functional Description
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DC Electrical Characteristics
Absolute Maximum Ratings
Table 3:
DC and Switching Characteristics
Power Supply Specifications
Table 4:
Table 7:
Table 6:
Table 5:
General DC Characteristics for I/O Pins
Table 8:
General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
I
VIN = VCCO VCCAUX = 3.0V to 3.6V 167 346 659 A
Quiescent Current Requirements
Table 9:
Quiescent Supply Current Characteristics
Single-Ended I/O Standards
Table 10:
Recommended Operating Conditions for User I/Os Using Single-Ended Standards
Table 11:
DC Characteristics of User I/Os Using Single-Ended Standards
DS610-3 (v2.0) July 16, 2007 www.xilinx.com 17
Differential I/O Standards
IOSTANDARD Attribute
Figure 3:
Table 12:
Differential Input Voltages
Figure 4:
V
VOUTP - VOUTN
= Output common mode voltage = 2
18 www.xilinx.com DS610-3 (v2.0) July 16, 2007
Device DNA Data Retention, Read Endurance
LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
Figure 5:
BLVDS_25 I/O Standard
Switching Characteristics
Software Version Requirements
Table 16:
I/O Timing
Table 17:
Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Table 18:
Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Table 19:
Setup and Hold Times for the IOB Input Path
Table 20:
Propagation Times for the IOB Input Path
Table 21:
Table 22:
Timing for the IOB Output Path
Table 23:
Set/Reset Times
Timing for the IOB Three-State Path
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Timing Measurement Methodology
Figure 8:
Table 25:
The capacitive load (CL) is connected between the output and GND.
Test Methods for Timing Measurement at I/Os
Table 25:
Using IBIS Models to Simulate Load Conditions in Application
Simultaneously Switching Output Guidelines
Table 26:
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Configurable Logic Block (CLB) Timing
Table 28:
CLB (SLICEM) Timing
Set/Reset Pulse Width
Clock Buffer/Multiplexer Switching Characteristics
Table 29:
Table 31:
Table 30:
CLB Distributed RAM Switching Characteristics
Block RAM Timing
Table 32:
Block RAM Timing
Clock Frequency
DSP48A Timing
XtremeDSP DSP48A for Spartan-3A DSP FPGA User Guide
Table 33:
To reference the DSP48A block diagram, see the
(UG431).
Table 34:
Clock to Out, Propagation Delays, and Maximum Frequency for the DSP48A
Clock to Out from Output Register Clock to Output Pin
Clock to Out from Pipeline Register Clock to Output Pins
Clock to Out from Input Register Clock to Output Pins
Digital Clock Manager (DCM) Timing
Delay-Locked Loop (DLL)
Table 35:
Table 36:
42 www.xilinx.com DS610-3 (v2.0) July 16, 2007
Switching Characteristics for the DLL
Notes:
DS610-3 (v2.0) July 16, 2007 www.xilinx.com 43
Digital Frequency Synthesizer (DFS)
Symbol Description
Table 38:
Table 37:
Recommended Operating Conditions for the DFS
Phase Shifter (PS)
Table 39:
Table 41:
Table 40:
Miscellaneous DCM Timing
DNA Port Timing
Table 42:
DNA_PORT Interface Timing
Suspend Mode Timing
t
sw_gts_cycle:512
sw_gts_cycle:1
sw_gwe_cycle:512
Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
(Open-Drain)
(Output)
Table 44:
Configuration Clock (CCLK) Characteristics
ConfigRate
(power-on value)
Master Mode CCLK Output Period by
Table 45:
Table 46:
ConfigRate
Table 48:
Table 47:
(power-on value)
Master Serial and Slave Serial Mode Timing
Figure 11:
Table 49:
Waveforms for Master Serial and Slave Serial Configuration
Timing for the Master Serial and Slave Serial Configuration Modes
Slave Parallel Mode Timing
Figure 12:
Table 50:
Waveforms for Slave Parallel Configuration
Timing for the Slave Parallel Configuration Mode
Serial Peripheral Interface (SPI) Configuration Timing
Figure 13:
Table 51:
Waveforms for Serial Peripheral Interface (SPI) Configuration
Timing for Serial Peripheral Interface (SPI) Configuration Mode
Table 52:
Configuration Timing Requirements for Attached SPI Serial Flash
---------------------------------
f
TVTMCCLn TDCC
Byte Peripheral Interface (BPI) Configuration Timing
Figure 14:
Table 53:
Waveforms for Byte-wide Peripheral Interface (BPI) Configuration
Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
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IEEE 1149.1/1553 JTAG Test Access Port Timing
JTAG Waveforms
Table 55:
Figure 15:
TCK
The following table shows the revision history for this document.
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Packaging
Pin Types
Table 56:
Pinout Descriptions
Package Pins by Type
Table 56:
Table 58:
Table 57:
Package Thermal Characteristics
Table 59:
CS484: 484-Ball Chip-Scale Ball Grid Array
Spartan-3A DSP CS484 Pinout
.
Pinout Table
Spartan-3A DSP CS484 Pinout
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User I/Os by Bank
Table 61:
Table 62:
Footprint Migration Differences
DS610-4 (v2.0) July 16, 2007 www.xilinx.com 69
CS484 Footprint
Bank 2
B
Bank 3
M
Right Half of CS484 Package (top view)
12 13 14 15 16 17 18 19 20 21 22
Bank 2
C
D
FG676: 676-Ball Fine-Pitch Ball Grid Array
list of differences and migration advice, see the "Footprint Migration Differences" section.
XC3SD1800A FPGA
Pinout Table
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Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA
Bank XC3SD1800A Pin Name FG676
Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA
Bank XC3SD1800A Pin Name FG676
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User I/Os by Bank
Table 64:
DS610-4 (v2.0) July 16, 2007 www.xilinx.com 81
FG676 Footprint
Bank 2
E
D
C
Right Half of FG676 Package (top view)
14 15 16 17 18 19 20 21 22 23 24 25 26
U
B
C
XC3SD3400A FPGA
Pinout Table
Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA
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Bank XC3SD3400A Pin Name FG676
User I/Os by Bank
Table 66:
DS610-4 (v2.0) July 16, 2007 www.xilinx.com 93
FG676 Footprint
F
A
R
P
Right Half of FG676 Package (top view)
14 15 16 17 18 19 20 21 22 23 24 25 26
U
H
J
Footprint Migration Differences
Table 67:
FG676 Footprint Migration Differences
Migration Recommendations
FG676 Footprint Migration Differences
Table 67:
The following table shows the revision history for this document.
SPARTAN-3A DSP
www.xilinx.com/spartan3adsp
Date Version Revision
