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Introduction and Ordering Information
R
Architectural Overview
The
•XtremeDSP DSP48A Slice provides an
•Block RAM provides data storage in the form of
•Configurable Logic Blocks (CLBs) contain flexible
•Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. IOBs support bidirectional data flow plus
•Digital Clock Manager (DCM) Blocks provide
These elements are organized as shown in Figure 1. A dual ring of staggered IOBs surrounds a regular array of CLBs. The XC3SD1800A has four columns of DSP48As, and the XC3SD3400A has five columns of DSP48As. Each DSP48A has an associated block RAM. The DCMs are positioned in the center with two at the top and two at the bottom of the device and in the two outer columns of the 4 or 5 columns of block RAM and DSP48As.
The
After applying power, the configuration data is written to the FPGA using any of seven different modes:
•Master Serial from a Xilinx Platform Flash PROM
•Serial Peripheral Interface (SPI) from an
•Byte Peripheral Interface (BPI) Up from an
•Slave Serial, typically downloaded from a processor
•Slave Parallel, typically downloaded from a processor
•Boundary Scan (JTAG), typically downloaded from a processor or system tester
Furthermore,
Additionally, each
I/O Capabilities
The
•3.3V
•
•3.3V PCI at 33 MHz or 66 MHz
•HSTL I, II, and III at 1.5V and 1.8V, commonly used in memory applications
Configuration
•SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used for memory applications
•LVDS,
•Bus LVDS I/O at 2.5V
•TMDS I/O at 3.3V
•Differential HSTL and SSTL I/O
•LVPECL inputs at 2.5V or 3.3V
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