Right Half of CS484 Package top view | Xilinx DS610 manual

Pinout Descriptions

R

Bank 0

12

13

14

15

16

17

18

19

20

21

22

INPUT

I/O

I/O

INPUT

I/O

I/O

INPUT

I/O

I/O

TCK

GND

A

L06P_0

L11P_0

L10P_0

L06N_0

L07N_0

0

VREF_0

GND

I/O

VCCO_0

I/O

GND

I/O

VCCO_0

I/O

I/O

VCCAUX

TDO

B

L11N_0

L10N_0

L03P_0

L02N_0

L07P_0

I/O

I/O

INPUT

I/O

I/O

I/O

I/O

I/O

GND

INPUT

INPUT

C

L12N_0

L02P_0

L39P_1

L14N_0

L14P_0

L08N_0

L03N_0

L01N_0

L39N_1

VREF_0

VREF_0

VREF_1

VCCAUX

I/O

I/O

I/O

GND

INPUT

INPUT

I/O

I/O

I/O

I/O

D

L36P_1

L37P_1

L37N_1

L09N_0

L12P_0

L08P_0

L01P_0

A20

A22

A23

I/O

I/O

VCCO_0

I/O

I/O

INPUT

VCCAUX

I/O

I/O

VCCO_1

I/O

E

L17P_0

L36N_1

L09P_0

L05P_0

L04P_0

L35N_1

L33N_1

GCLK4

A21

INPUT

I/O

I/O

I/O

I/O

GND

I/O

I/O

I/O

I/O

I/O

F

L38N_1

L38P_1

L30N_1

L13N_0

L13P_0

L05N_0

L04N_0

L35P_1

L33P_1

A25

A24

A19

VCCAUX

GND

VCCAUX

GND

VCCINT

I/O

I/O

I/O

INPUT

GND

I/O

G

L30P_1

L34P_1

L34N_1

L31N_1

L28N_1

A18

GND

VCCINT

GND

VCCINT

GND

I/O

I/O

GND

I/O

INPUT

I/O

H

L26P_1

L26N_1

L31P_1

L32N_1

L28P_1

A14

A15

VREF_1

VCCINT

GND

VCCINT

GND

VCCAUX

I/O

VCCO_1

I/O

I/O

INPUT

INPUT

J

L29N_1

L25N_1

L32P_1

L27P_1

L27N_1

A17

A13

GND

VCCINT

GND

VCCINT

I/O

INPUT

I/O

I/O

I/O

VCCO_1

I/O

K

L29P_1

L25P_1

L22N_1

L23N_1

L24N_1

L24P_1

A16

A12

A11

VCCINT

GND

VCCINT

GND

VCCAUX

I/O

INPUT

GND

I/O

I/O

I/O

L

L21N_1

L23P_1

L20N_1

L20P_1

L22P_1

RHCLK7

VREF_1

RHCLK5

RHCLK4

A10

I/O

I/O

I/O

I/O

GND

VCCINT

GND

VCCINT

GND

L21P_1

VCCAUX

L19N_1

GND

M

L18N_1

L17N_1

IRDY1

TRDY1

RHCLK1

A9

RHCLK6

RHCLK3

VCCINT

GND

VCCINT

GND

VCCAUX

I/O

I/O

I/O

I/O

I/O

I/O

N

L13P_1

L18P_1

L15N_1

L15P_1

L19P_1

L17P_1

A2

RHCLK0

A7

A6

RHCLK2

A8

GND

VCCINT

GND

VCCINT

I/O

INPUT

VCCO_1

I/O

INPUT

VCCO_1

I/O

P

L13N_1

L12N_1

L14N_1

L10P_1

L16N_1

A3

VREF_1

A5

VCCINT

GND

VCCINT

GND

GND

INPUT

I/O

I/O

I/O

INPUT

I/O

R

L16P_1

L14P_1

L12P_1

L10N_1

L07P_1

L07N_1

VREF_1

A4

GND

VCCAUX

GND

GND

VCCINT

I/O

I/O

GND

I/O

GND

I/O

T

L11N_1

L05N_1

L05P_1

L09N_1

VREF_1

I/O

I/O

I/O

I/O

I/O

GND

I/O

I/O

I/O

INPUT

I/O

U

L17P_2

L01P_1

L01N_1

L08N_1

L20P_2

L25P_2

L25N_2

L28P_2

L09P_1

L11P_1

GCLK0

HDC

LDC2

VREF_1

I/O

I/O

INPUT

I/O

I/O

SUSPEN

I/O

INPUT

L20N_2

VCCO_2

VCCAUX

VCCO_1

V

L17N_2

2

L31N_2

L03N_1

MOSI

L28N_2

D

L08P_1

GCLK1

CSI B

VREF_2

CCLK

A1

INPUT

I/O

I/O

I/O

INPUT

I/O

INPUT

INPUT

I/O

GND

GND

L31P_2

W

2

L24P_2

2

L03P_1

L04N_1

L21N_2

D0

L04P_1

L06P_1

VREF_2

INIT_B

DIN/MISO

VREF_2

A0

VREF_1

INPUT

I/O

INPUT

I/O

I/O

I/O

I/O

I/O

GND

I/O

I/O

Y

2

L24N_2

L26P_2

L26N_2

L02P_1

L21P_2

L29N_2

L29P_2

L06N_1

VREF_2

D3

D2

D1

LDC1

I/O

VCCO_2

I/O

I/O

GND

I/O

VCCO_2

I/O

I/O

VCCAUX

I/O

A

L16P_2

L18N_2

L19P_2

L22P_2

L27N_2

L30P_2

L02N_1

A

GCLK14

GCLK3

AWAKE

LDC0

I/O

I/O

I/O

INPUT

I/O

I/O

I/O

I/O

I/O

DONE

GND

A

L16N_2

L18P_2

L19N_2

L22N_2

L23P_2

L23N_2

L27P_2

L30N_2

B

GCLK15

GCLK2

DOUT

Bank 2

Right Half of CS484 Package (top view)

70	www.xilinx.com	DS610-4 (v2.0) July 16, 2007
		Product Specification

Image 70

Xilinx DS610 manual Right Half of CS484 Package top view

Contents

DS610-2 v2.0 July 16 Product SpecificationDS610-1 v2.0 July 16 DS610-3 v2.0 July 16 Data Sheet Introduction FeaturesSpartan-3A and Spartan-3A DSP Fpga Differences Capabilities ConfigurationArchitectural Overview Introduction and Ordering Information 519 227 DCMCS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A XC3SD3400A Standard Packaging Package MarkingOrdering Information Pb-Free Packaging Revision History Date Version Revision Introduction and Ordering Information Added Low-power options no changes to this module DS610-2 v2.0 July 16 Functional Description Absolute Maximum Ratings DC Electrical CharacteristicsSymbol Description Conditions Min Max Units Absolute Maximum Ratings Supply Voltage Thresholds for Power-On Reset Power Supply SpecificationsDC and Switching Characteristics Symbol Description Min Max Units Symbol Description Test Conditions Min Typ Max Units General DC Characteristics for I/O Pins= GND Quiescent Current Requirements Quiescent Supply Current CharacteristicsTypical2 Commercial Industrial Symbol Description Device Maximum2 CCO for Drivers Single-Ended I/O StandardsAttribute Min Nom Max Test Logic Level Conditions Test Logic Level Conditions CharacteristicsAttribute Attribute Max Min Iostandard Attribute CCO for Drivers Differential I/O StandardsMin Nom Max Min mV Nom mV Max mV Iostandard Attribute Min mV Typ mV Max mV Device DNA Data Retention, Read Endurance Device DNA Identifier Memory CharacteristicsSymbol Description Minimum Units External Termination Requirements for Differential I/O Switching Characteristics Software Version Requirements Spartan-3A DSP Speed File Version History Sign Up for Alerts on Xilinx MySupportSpartan-3A DSP v1.29 Speed Grade Designations Rate, without DCM TimingPin-to-Pin Clock-to-Output Times for the IOB Output Path At the Output pin. The DCM is not Use Ifddelayvalue = Hold Times Set/Reset Pulse Width Symbol Description ConditionsDevice Min Units Setup Times Speed Grade Ioplid PCI333 PCI663 Single-Ended StandardsLvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 Differential Standards Asynchronous Output Enable/Disable Times Set/Reset TimesTiming for the IOB Three-State Path QuietIO 27.67 QuietIO QuietIO 25.92 QuietIO 24.97 LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25 Inputs Only Test Methods for Timing Measurement at I/Os Signal Standard Inputs OutputsTiming Measurement Methodology Inputs Differential RT ΩVicm + Equivalent VCCO/GND Pairs per Bank Simultaneously Switching Output GuidelinesDevice CS484 FG676 XC3SD1800A XC3SD3400A Package Type Signal Standard Top, Bottom Left, RightCS484, FG676 QuietIO PCI333 PCI663 Differential Standards Number of I/O Pairs or Channels CLB Slicem Timing Configurable Logic Block CLB TimingClock Timing CLB Shift Register Switching Characteristics Clock Buffer/Multiplexer Switching CharacteristicsClock Distribution Switching Characteristics Block RAM Timing Block RAM TimingClock Frequency Setup Times of Data Pins to the Pipeline Register Clock Setup Times for the DSP48ASpeed Grade Symbol Description DSP48A Timing Combinatorial Delays from Input Pins to Output Pins Clock to Out from Pipeline Register Clock to Output PinsClock to Out from Input Register Clock to Output Pins Maximum Frequency Digital Clock Manager DCM Timing Delay-Locked Loop DLLInput Clock Jitter Tolerance Delay Path Variation4 Recommended Operating Conditions for the DLL Speed Grade Symbol Description Digital Frequency Synthesizer DFS Switching Characteristics for the DFSSpeed Grade Symbol Description Units Min Max Recommended Operating Conditions for the DFS Phase Shifting Range Phase Shifter PSSwitching Characteristics for the PS in Variable Phase Mode Miscellaneous DCM Timing DNA Port Timing Dnaport Interface Timing Entering Suspend Mode Suspend Mode TimingEntering Suspend Mode Exiting Suspend Mode Symbol Description Min Typ Max Units General Configuration Power-On/Reconfigure Timing Configuration and Jtag TimingAll Speed Grades Symbol Description Device Min Max Units Cclk clock period by Configuration Clock Cclk CharacteristicsMaster Mode Cclk Output Period by ConfigRate Option Setting 11.2 Equivalent Cclk clock frequency Master Mode Cclk Output Minimum Low and High TimeSlave Mode Cclk Input Low and High Time Cclk Low and High time Slave All Speed Grades Symbol Description Master Serial and Slave Serial Mode TimingMin Max Units Clock-to-Output Times Slave Parallel Mode Timing Serial Peripheral Interface SPI Configuration Timing Symbol Description Minimum Symbol Description Requirement Units Setup time on M20 mode pins before the rising edge of Initb Byte Peripheral Interface BPI Configuration TimingSymbol Description Minimum Maximum Units Hold time on M20 mode pins after the rising edge of Initb Parallel NOR Flash Prom read access time Symbol Description Requirement UnitsParallel NOR Flash Prom output-enable time Parallel NOR Flash Prom chip-select time Ieee 1149.1/1553 Jtag Test Access Port Timing INTEST, EXTEST, Sample Diffhstli and Diffhstliii to , , and . Updated Tmds DC DSP48A timing in and Table DC and Switching Characteristics Pin Types Types of Pins on Spartan-3A DSP FPGAsType/Color Description Pin Names in Type Code Power and Ground Supply Pins by Package Package Pins by TypePinout Descriptions Types of Pins on Spartan-3A DSP FPGAs Maximum User I/O by Package Spartan-3A DSP Package Thermal Characteristics Package Thermal CharacteristicsPinout Descriptions Spartan-3A DSP CS484 Pinout CS484 484-Ball Chip-Scale Ball Grid ArrayPinout Table Bank Pin Name CS484 Type Ball Pinout Descriptions Spartan-3A DSP CS484 Pinout AA4 VCCO1AA3 Dual AA6 Input VCCO2 Vcco VCCO2 AA5 Vcco AA9VCCO2 AA1 Vref GND AA7 VCCO3 VccoGND AB1 Jtag Vccaux Progb Config DoneVccaux TCK Vccaux TMS Jtag TDO User I/Os Per Bank for the XC3SD1800A in the CS484 Package User I/Os by BankFootprint Migration Differences User I/Os Per Bank for the XC3SD3400A in the CS484 Package CS484 Footprint Left Half of Package top view Right Half of CS484 Package top view Spartan-3A DSP FG676 Pinout for FG676 676-Ball Fine-Pitch Ball Grid ArrayPinout Table Spartan-3A DSP FG676 Pinout for XC3SD1800A Fpga IOL26P0/GCLK6 IOL26N0/GCLK7 IOL33P1/RHCLK4 IOL30N1/RHCLK1IOL30P1/RHCLK0 IOL31P1/RHCLK2 IOL17P2/RDWRB IOL27P2/GCLK0 AF5 AF3AF4 AF7 Input IOL30N2/MOSI/CSIB IP2/VREF2 AB6 VrefAB9 IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 Vref IOL34P3/LHCLK4 IOL33P3/LHCLK2IOL34N3/LHCLK5 IOL35N3/LHCLK7 AD1 AE1 InputAE2 Vref AD2 GND AD3 AD8 Vccaux Progb Config TDI Jtag TDOGND AF1 AF6 GND AA1 AA6 Top 128 Right User I/Os by BankUser I/Os Per Bank for the XC3SD1800A in the FG676 Package 519 314 FG676 Footprint FG676 Package Footprint for XC3SD1800A Fpga top view TDO IOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0 Spartan-3A DSP FG676 Pinout for XC3SD3400A FpgaBank XC3SD3400A Pin Name FG676 Type Ball IOL01P0 G20 VCCO0 Vcco IOL01P1/HDC IP1/VREF1 IOL34P1/IRDY1/RHCLK6 IOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16 T25 IOL05N1 AC25 IOL06P1IOL12P2 Y10 IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17 VCCO2 AF7 Vcco AE5 IOL36N3 IOL37P3 IOL53P3 IOL53N3 IP3IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IOL10N3 IOL03N3 IP3 IP3/VREF3 VrefAA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND GND AB3 GND AD3 AD5 AD8GND AC5 AC7 GND AA1 AA4 AA6 Vccaux AF2 AB4 AB5 Vccint AA8 Top 111 Right Vref are on Input pinsUser I/Os Per Bank for the XC3SD3400A in the FG676 Package Bottom 112 Left FG676 Package Footprint for XC3SD3400A Fpga top view Pinout Descriptions VCCO0 VREF1 FG676 Footprint Migration Differences VREF1 Migration Recommendations Pinout Descriptions FG676 Footprint Migration Differences SPARTAN-3A DSP Fpga and XC3SD3400A Fpga . Minor edits Pinout Descriptions