Xilinx DS610 manual Ifddelayvalue =, Hold Times

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DC and Switching Characteristics

Table 18: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)

				Speed Grade
				-5	-4
Symbol	Description	Conditions	Device	Min	Min	Units
Setup Times
TPSDCM	When writing to the Input	LVCMOS25(2),	XC3SD1800A	2.65	3.11	ns
	Flip-Flop (IFF), the time from	IFD_DELAY_VALUE = 0,
			XC3SD3400A	2.25	2.49	ns
	the setup of data at the Input	with DCM(4)
	pin to the active transition at a
	Global Clock pin. The DCM is in
	use. No Input Delay is
	programmed.
TPSFD	When writing to IFF, the time	LVCMOS25(2),	XC3SD1800A	2.98	3.39	ns
	from the setup of data at the	IFD_DELAY_VALUE = 6,
			XC3SD3400A	2.78	3.08	ns
	Input pin to an active transition	without DCM
	at the Global Clock pin. The
	DCM is not in use. The Input
	Delay is programmed.
Hold Times
T	When writing to IFF, the time	LVCMOS25(3),	XC3SD1800A	-0.38	-0.38	ns
PHDCM	from the active transition at the	IFD_DELAY_VALUE = 0,
			XC3SD3400A	-0.26	-0.26	ns
	Global Clock pin to the point	with DCM(4)
	when data must be held at the
	Input pin. The DCM is in use.
	No Input Delay is programmed.
TPHFD	When writing to IFF, the time	LVCMOS25(3),	XC3SD1800A	-0.71	-0.71	ns
	from the active transition at the	IFD_DELAY_VALUE = 6,
			XC3SD3400A	-0.65	-0.65	ns
	Global Clock pin to the point	without DCM
	when data must be held at the
	Input pin. The DCM is not in
	use. The Input Delay is
	programmed.
Notes:

1.The numbers in this table are tested using the methodology presented in Table 25 and are based on the operating conditions set forth in Table 7 and Table 10.

2.This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 21. If this is true of the data Input, add the appropriate Input adjustment from the same table.

3.This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 21. If this is true of the data Input, subtract the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active edge.

4.DCM output jitter is included in all measurements.

DS610-3 (v2.0) July 16, 2007 www.xilinx.com 23

Product Specification