DC and Switching Characteristics
R
IEEE 1149.1/1553 JTAG Test Access Port Timing
TCK (Input)
TTMSTCK
TMS (Input)
TTDITCK
TDI (Input)
TDO (Output)
TCCH | TCCL |
TTCKTMS | 1/FTCK |
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TTCKTDI |
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TTCKTDO |
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| DS099_06_040703 |
Figure 15: JTAG Waveforms
Table 55: Timing for the JTAG Test Access Port
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| All Speed |
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| Grades |
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Symbol |
| Description | Min | Max | Units |
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TTCKTDO | The time from the falling transition on the TCK pin to data appearing at the TDO pin | 1.0 | 11.0 | ns | |
Setup Times |
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TTDITCK | The time from the setup of data at the | All functions except those shown below | 7.0 | – | ns |
| TDI pin to the rising transition at the |
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| Boundary scan commands | 13.0 |
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| TCK pin |
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| (INTEST, EXTEST, SAMPLE) |
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TTMSTCK | The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin | 7.0 | – | ns | |
Hold Times |
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TTCKTDI | The time from the rising transition at | All functions except those shown below | 0 | – | ns |
| the TCK pin to the point when data is |
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| Configuration commands (CFG_IN, ISC_PROGRAM) | 3.5 |
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| last held at the TDI pin |
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TTCKTMS | The time from the rising transition at the TCK pin to the point when a logic level is last held at the | 0 | – | ns | |
| TMS pin |
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Clock Timing |
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TCCH | The High pulse width at the TCK pin | All functions except ISC_DNA command | 5 | – | ns |
TCCL | The Low pulse width at the TCK pin |
| 5 | – | ns |
TCCHDNA | The High pulse width at the TCK pin | During ISC_DNA command | 10 | 10,000 | ns |
TCCLDNA | The Low pulse width at the TCK pin |
| 10 | 10,000 | ns |
FTCK | Frequency of the TCK signal | BYPASS or HIGHZ instructions | 0 | 33 | MHz |
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| All operations except for BYPASS or HIGHZ instructions |
| 20 |
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Notes:
1.The numbers in this table are based on the operating conditions set forth in Table 7.
56 | www.xilinx.com | |
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| Product Specification |