DSP48A timing in and Table | Xilinx DS610 specification

R

DC and Switching Characteristics

Revision History

The following table shows the revision history for this document.

Date	Version	Revision
04/02/07	1.0	Initial Xilinx release.

05/25/07	1.0.1	Minor edits.

06/18/07	1.2	Updated for v1.29 production speed files. Noted banking rules in Table 11 and Table 12. Added
		DIFF_HSTL_I and DIFF_HSTL_III to Table 12, Table 13, and Table 25. Updated TMDS DC
		characteristics in Table 13. Updated I/O Test Method values in Table 25. Added Simultaneously
		Switching Output limits in Table 27. Updated DSP48A timing symbols, descriptions, and values in
		Table 33. Added power-on timing in Table 44. Added CCLK specifications for Commercial in Table 45
		through Table 47. Updated Slave Parallel timing in Table 50. Updated JTAG specifications in Table 55.

07/16/07	2.0	Added Low-power options and updated typical values for quiescent current in Table 9. Updated
		DSP48A timing in Table 33 and Table 34.

DS610-3 (v2.0) July 16, 2007

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Product Specification

Image 57

Xilinx DS610 manual Diffhstli and Diffhstliii to , , and . Updated Tmds DC, DSP48A timing in and Table

Contents

DS610-1 v2.0 July 16 Product SpecificationDS610-2 v2.0 July 16 DS610-3 v2.0 July 16 Data Sheet Features IntroductionSpartan-3A and Spartan-3A DSP Fpga Differences Architectural Overview ConfigurationCapabilities Introduction and Ordering Information CS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A DCM519 227 XC3SD3400A Ordering Information Package MarkingStandard Packaging Pb-Free Packaging Date Version Revision Revision History Introduction and Ordering Information DS610-2 v2.0 July 16 Added Low-power options no changes to this module Functional Description Symbol Description Conditions Min Max Units DC Electrical CharacteristicsAbsolute Maximum Ratings Absolute Maximum Ratings DC and Switching Characteristics Power Supply SpecificationsSupply Voltage Thresholds for Power-On Reset Symbol Description Min Max Units General DC Characteristics for I/O Pins Symbol Description Test Conditions Min Typ Max Units= GND Typical2 Commercial Industrial Symbol Description Device Quiescent Supply Current CharacteristicsQuiescent Current Requirements Maximum2 Single-Ended I/O Standards CCO for DriversAttribute Min Nom Max Attribute Test Logic Level Conditions CharacteristicsTest Logic Level Conditions Attribute Max Min Differential I/O Standards Iostandard Attribute CCO for DriversMin Nom Max Min mV Nom mV Max mV Iostandard Attribute Min mV Typ mV Max mV Symbol Description Minimum Units Device DNA Identifier Memory CharacteristicsDevice DNA Data Retention, Read Endurance External Termination Requirements for Differential I/O Software Version Requirements Switching Characteristics Sign Up for Alerts on Xilinx MySupport Spartan-3A DSP Speed File Version HistorySpartan-3A DSP v1.29 Speed Grade Designations Pin-to-Pin Clock-to-Output Times for the IOB Output Path TimingRate, without DCM At the Output pin. The DCM is not Use Hold Times Ifddelayvalue = Device Min Units Setup Times Symbol Description ConditionsSet/Reset Pulse Width Speed Grade Ioplid Lvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 Single-Ended StandardsPCI333 PCI663 Differential Standards Set/Reset Times Asynchronous Output Enable/Disable TimesTiming for the IOB Three-State Path QuietIO QuietIO 27.67 QuietIO 24.97 QuietIO 25.92 Inputs Only LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25 Timing Measurement Methodology Signal Standard Inputs OutputsTest Methods for Timing Measurement at I/Os Inputs RT Ω DifferentialVicm + Simultaneously Switching Output Guidelines Equivalent VCCO/GND Pairs per BankDevice CS484 FG676 XC3SD1800A XC3SD3400A Signal Standard Top, Bottom Left, Right Package TypeCS484, FG676 Differential Standards Number of I/O Pairs or Channels QuietIO PCI333 PCI663 Configurable Logic Block CLB Timing CLB Slicem TimingClock Timing Clock Buffer/Multiplexer Switching Characteristics CLB Shift Register Switching CharacteristicsClock Distribution Switching Characteristics Block RAM Timing Block RAM TimingClock Frequency Speed Grade Symbol Description Setup Times for the DSP48ASetup Times of Data Pins to the Pipeline Register Clock DSP48A Timing Clock to Out from Input Register Clock to Output Pins Clock to Out from Pipeline Register Clock to Output PinsCombinatorial Delays from Input Pins to Output Pins Maximum Frequency Input Clock Jitter Tolerance Delay Path Variation4 Delay-Locked Loop DLLDigital Clock Manager DCM Timing Recommended Operating Conditions for the DLL Speed Grade Symbol Description Speed Grade Symbol Description Units Min Max Switching Characteristics for the DFSDigital Frequency Synthesizer DFS Recommended Operating Conditions for the DFS Switching Characteristics for the PS in Variable Phase Mode Phase Shifter PSPhase Shifting Range Miscellaneous DCM Timing Dnaport Interface Timing DNA Port Timing Entering Suspend Mode Exiting Suspend Mode Suspend Mode TimingEntering Suspend Mode Symbol Description Min Typ Max Units Configuration and Jtag Timing General Configuration Power-On/Reconfigure TimingAll Speed Grades Symbol Description Device Min Max Units Master Mode Cclk Output Period by ConfigRate Option Setting Configuration Clock Cclk CharacteristicsCclk clock period by 11.2 Slave Mode Cclk Input Low and High Time Master Mode Cclk Output Minimum Low and High TimeEquivalent Cclk clock frequency Cclk Low and High time Master Serial and Slave Serial Mode Timing Slave All Speed Grades Symbol DescriptionMin Max Units Clock-to-Output Times Slave Parallel Mode Timing Symbol Description Minimum Serial Peripheral Interface SPI Configuration Timing Symbol Description Requirement Units Symbol Description Minimum Maximum Units Byte Peripheral Interface BPI Configuration TimingSetup time on M20 mode pins before the rising edge of Initb Hold time on M20 mode pins after the rising edge of Initb Parallel NOR Flash Prom output-enable time Symbol Description Requirement UnitsParallel NOR Flash Prom read access time Parallel NOR Flash Prom chip-select time INTEST, EXTEST, Sample Ieee 1149.1/1553 Jtag Test Access Port Timing DSP48A timing in and Table Diffhstli and Diffhstliii to , , and . Updated Tmds DC DC and Switching Characteristics Types of Pins on Spartan-3A DSP FPGAs Pin TypesType/Color Description Pin Names in Type Code Pinout Descriptions Types of Pins on Spartan-3A DSP FPGAs Package Pins by TypePower and Ground Supply Pins by Package Maximum User I/O by Package Package Thermal Characteristics Spartan-3A DSP Package Thermal CharacteristicsPinout Descriptions Pinout Table CS484 484-Ball Chip-Scale Ball Grid ArraySpartan-3A DSP CS484 Pinout Bank Pin Name CS484 Type Ball Pinout Descriptions Spartan-3A DSP CS484 Pinout AA3 Dual VCCO1AA4 AA6 Input VCCO2 VCCO2 AA5 Vcco AA9VCCO2 Vcco AA1 Vref VCCO3 Vcco GND AA7GND AB1 Vccaux TCK Vccaux Progb Config DoneJtag Vccaux TMS Jtag TDO Footprint Migration Differences User I/Os by BankUser I/Os Per Bank for the XC3SD1800A in the CS484 Package User I/Os Per Bank for the XC3SD3400A in the CS484 Package Left Half of Package top view CS484 Footprint Right Half of CS484 Package top view Pinout Table FG676 676-Ball Fine-Pitch Ball Grid ArraySpartan-3A DSP FG676 Pinout for Spartan-3A DSP FG676 Pinout for XC3SD1800A Fpga IOL26N0/GCLK7 IOL26P0/GCLK6 IOL30P1/RHCLK0 IOL30N1/RHCLK1IOL33P1/RHCLK4 IOL31P1/RHCLK2 IOL27P2/GCLK0 IOL17P2/RDWRB AF4 AF3AF5 AF7 Input AB9 IP2/VREF2 AB6 VrefIOL30N2/MOSI/CSIB IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 Vref IOL34N3/LHCLK5 IOL33P3/LHCLK2IOL34P3/LHCLK4 IOL35N3/LHCLK7 AE2 Vref AE1 InputAD1 AD2 GND AF1 AF6 Vccaux Progb Config TDI Jtag TDOGND AD3 AD8 GND AA1 AA6 User I/Os Per Bank for the XC3SD1800A in the FG676 Package User I/Os by BankTop 128 Right 519 314 FG676 Package Footprint for XC3SD1800A Fpga top view FG676 Footprint TDO Bank XC3SD3400A Pin Name FG676 Type Ball Spartan-3A DSP FG676 Pinout for XC3SD3400A FpgaIOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0 IOL01P0 G20 IP1/VREF1 VCCO0 Vcco IOL01P1/HDC IOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16 IOL34P1/IRDY1/RHCLK6 IOL05N1 AC25 IOL06P1 T25IOL12P2 Y10 IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22 VCCO2 AF7 Vcco AE5 IOL53P3 IOL53N3 IP3 IOL36N3 IOL37P3IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IP3/VREF3 Vref IOL10N3 IOL03N3 IP3AA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND GND AC5 AC7 GND AD3 AD5 AD8GND AB3 GND AA1 AA4 AA6 Vccint AA8 Vccaux AF2 AB4 AB5 User I/Os Per Bank for the XC3SD3400A in the FG676 Package Vref are on Input pinsTop 111 Right Bottom 112 Left Pinout Descriptions FG676 Package Footprint for XC3SD3400A Fpga top view VCCO0 VREF1 VREF1 FG676 Footprint Migration Differences Pinout Descriptions FG676 Footprint Migration Differences Migration Recommendations Fpga and XC3SD3400A Fpga . Minor edits SPARTAN-3A DSP Pinout Descriptions