VCCO2 AA5 Vcco AA9, VCCO2 Vcco, AA1 Vref | Xilinx DS610 manual

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Pinout Descriptions

Table 60: Spartan-3A DSP CS484 Pinout (Continued)

	Bank	Pin Name	CS484	Type
	Bank	Pin Name	Ball	Type
			Ball
	2	IP_2/VREF_2	Y14	VREF

	2	IO_L24N_2/D3	Y15	DUAL

	2	IO_L29N_2	Y16	I/O

	2	IO_L29P_2	Y17	I/O

	2	IO_L26P_2/D2	Y18	DUAL

	2	IO_L26N_2/D1	Y19	DUAL

	2	VCCO_2	AA5	VCCO

	2	VCCO_2	AA9	VCCO

	2	VCCO_2	AA13	VCCO

	2	VCCO_2	AA18	VCCO

	2	VCCO_2	V9	VCCO

	2	VCCO_2	V14	VCCO

	3	IP_L39N_3/VREF_3	AA1	VREF

	3	IO_L02N_3	C1	I/O

	3	IO_L02P_3	C2	I/O

	3	IP_L04P_3	D1	INPUT

	3	IP_L08P_3	D3	INPUT

	3	IP_L08N_3	D4	INPUT

	3	IP_L04N_3/VREF_3	E1	VREF

	3	IO_L09P_3	E3	I/O

	3	IO_L09N_3	E4	I/O

	3	IO_L06N_3	F1	I/O

	3	IO_L06P_3	F2	I/O

	3	IO_L01P_3	F3	I/O

	3	IO_L03P_3	F4	I/O

	3	IO_L03N_3	F5	I/O

	3	IO_L11P_3	G1	I/O

	3	IO_L01N_3	G3	I/O

	3	IO_L07P_3	G5	I/O

	3	IO_L07N_3	G6	I/O

	3	IO_L11N_3	H1	I/O

	3	IO_L14P_3	H2	I/O

	3	IO_L05P_3	H3	I/O

	3	IO_L05N_3	H4	I/O

	3	IO_L10P_3	H5	I/O

	3	IO_L10N_3	H6	I/O

	3	IO_L14N_3/VREF_3	J1	VREF

	3	IP_L16P_3	J3	INPUT

	3	IP_L16N_3	J4	INPUT

	3	IP_L12P_3	J6	INPUT

	3	IP_L12N_3/VREF_3	J7	VREF

	3	IO_L19P_3/LHCLK2	K1	LHCLK

Table 60: Spartan-3A DSP CS484 Pinout (Continued)

	Bank	Pin Name	CS484	Type
	Bank	Pin Name	Ball	Type
			Ball
	3	IO_L17P_3	K2	I/O

	3	IO_L17N_3	K3	I/O

	3	IO_L13P_3	K4	I/O

	3	IO_L13N_3	K5	I/O

	3	IO_L15P_3	K6	I/O

	3	IO_L19N_3/IRDY2/LHCLK3	L1	LHCLK

	3	IO_L20P_3/LHCLK4	L3	LHCLK

	3	IO_L15N_3	L5	I/O

	3	IO_L18P_3/LHCLK0	L6	LHCLK

	3	IO_L22P_3/VREF_3	M1	VREF

	3	IO_L20N_3/LHCLK5	M2	LHCLK

	3	IP_L23P_3	M3	INPUT

	3	IO_L18N_3/LHCLK1	M5	LHCLK

	3	IO_L21P_3/TRDY2/LHCLK6	M6	LHCLK

	3	IO_L22N_3	N1	I/O

	3	IP_L31P_3	N3	INPUT

	3	IP_L23N_3	N4	INPUT

	3	IO_L24N_3	N5	I/O

	3	IO_L24P_3	N6	I/O

	3	IO_L21N_3/LHCLK7	N7	LHCLK

	3	IO_L25P_3	P1	I/O

	3	IO_L25N_3	P2	I/O

	3	IP_L31N_3	P3	INPUT

	3	IO_L32P_3/VREF_3	P4	VREF

	3	IO_L26P_3	P6	I/O

	3	IO_L28N_3	R1	I/O

	3	IO_L28P_3	R2	I/O

	3	IO_L34P_3	R3	I/O

	3	IO_L32N_3	R5	I/O

	3	IO_L26N_3	R6	I/O

	3	IO_L30P_3	T1	I/O

	3	IP_L27P_3	T3	INPUT

	3	IO_L34N_3	T4	I/O

	3	IO_L29N_3	T5	I/O

	3	IO_L29P_3	T6	I/O

	3	IO_L30N_3	U1	I/O

	3	IO_L33P_3	U2	I/O

	3	IP_L27N_3	U3	INPUT

	3	IO_L38P_3	U4	I/O

	3	IO_L38N_3	U5	I/O

	3	IO_L33N_3	V1	I/O

	3	IO_L36N_3	V3	I/O

DS610-4 (v2.0) July 16, 2007

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65

Product Specification

Image 65

Xilinx DS610 VCCO2 AA5 Vcco AA9, VCCO2 Vcco, AA1 Vref, IOL19P3/LHCLK2 Lhclk, IOL19N3/IRDY2/LHCLK3 Lhclk IOL20P3/LHCLK4

Contents

DS610-1 v2.0 July 16 Product SpecificationDS610-2 v2.0 July 16 DS610-3 v2.0 July 16 Data Sheet Spartan-3A and Spartan-3A DSP Fpga Differences FeaturesIntroduction Architectural Overview ConfigurationCapabilities Introduction and Ordering Information CS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A DCM519 227 XC3SD3400A Ordering Information Package MarkingStandard Packaging Pb-Free Packaging Date Version Revision Revision History Introduction and Ordering Information DS610-2 v2.0 July 16 Added Low-power options no changes to this module Functional Description Symbol Description Conditions Min Max Units DC Electrical CharacteristicsAbsolute Maximum Ratings Absolute Maximum Ratings DC and Switching Characteristics Power Supply SpecificationsSupply Voltage Thresholds for Power-On Reset Symbol Description Min Max Units = GND General DC Characteristics for I/O PinsSymbol Description Test Conditions Min Typ Max Units Typical2 Commercial Industrial Symbol Description Device Quiescent Supply Current CharacteristicsQuiescent Current Requirements Maximum2 Attribute Min Nom Max Single-Ended I/O StandardsCCO for Drivers Attribute Test Logic Level Conditions CharacteristicsTest Logic Level Conditions Attribute Max Min Min Nom Max Min mV Nom mV Max mV Differential I/O StandardsIostandard Attribute CCO for Drivers Iostandard Attribute Min mV Typ mV Max mV Symbol Description Minimum Units Device DNA Identifier Memory CharacteristicsDevice DNA Data Retention, Read Endurance External Termination Requirements for Differential I/O Software Version Requirements Switching Characteristics Spartan-3A DSP v1.29 Speed Grade Designations Sign Up for Alerts on Xilinx MySupportSpartan-3A DSP Speed File Version History Pin-to-Pin Clock-to-Output Times for the IOB Output Path TimingRate, without DCM At the Output pin. The DCM is not Use Hold Times Ifddelayvalue = Device Min Units Setup Times Symbol Description ConditionsSet/Reset Pulse Width Speed Grade Ioplid Lvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 Single-Ended StandardsPCI333 PCI663 Differential Standards Timing for the IOB Three-State Path Set/Reset TimesAsynchronous Output Enable/Disable Times QuietIO QuietIO 27.67 QuietIO 24.97 QuietIO 25.92 Inputs Only LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25 Timing Measurement Methodology Signal Standard Inputs OutputsTest Methods for Timing Measurement at I/Os Inputs Vicm + RT ΩDifferential Device CS484 FG676 XC3SD1800A XC3SD3400A Simultaneously Switching Output GuidelinesEquivalent VCCO/GND Pairs per Bank CS484, FG676 Signal Standard Top, Bottom Left, RightPackage Type Differential Standards Number of I/O Pairs or Channels QuietIO PCI333 PCI663 Clock Timing Configurable Logic Block CLB TimingCLB Slicem Timing Clock Distribution Switching Characteristics Clock Buffer/Multiplexer Switching CharacteristicsCLB Shift Register Switching Characteristics Clock Frequency Block RAM TimingBlock RAM Timing Speed Grade Symbol Description Setup Times for the DSP48ASetup Times of Data Pins to the Pipeline Register Clock DSP48A Timing Clock to Out from Input Register Clock to Output Pins Clock to Out from Pipeline Register Clock to Output PinsCombinatorial Delays from Input Pins to Output Pins Maximum Frequency Input Clock Jitter Tolerance Delay Path Variation4 Delay-Locked Loop DLLDigital Clock Manager DCM Timing Recommended Operating Conditions for the DLL Speed Grade Symbol Description Speed Grade Symbol Description Units Min Max Switching Characteristics for the DFSDigital Frequency Synthesizer DFS Recommended Operating Conditions for the DFS Switching Characteristics for the PS in Variable Phase Mode Phase Shifter PSPhase Shifting Range Miscellaneous DCM Timing Dnaport Interface Timing DNA Port Timing Entering Suspend Mode Exiting Suspend Mode Suspend Mode TimingEntering Suspend Mode Symbol Description Min Typ Max Units All Speed Grades Symbol Description Device Min Max Units Configuration and Jtag TimingGeneral Configuration Power-On/Reconfigure Timing Master Mode Cclk Output Period by ConfigRate Option Setting Configuration Clock Cclk CharacteristicsCclk clock period by 11.2 Slave Mode Cclk Input Low and High Time Master Mode Cclk Output Minimum Low and High TimeEquivalent Cclk clock frequency Cclk Low and High time Min Max Units Clock-to-Output Times Master Serial and Slave Serial Mode TimingSlave All Speed Grades Symbol Description Slave Parallel Mode Timing Symbol Description Minimum Serial Peripheral Interface SPI Configuration Timing Symbol Description Requirement Units Symbol Description Minimum Maximum Units Byte Peripheral Interface BPI Configuration TimingSetup time on M20 mode pins before the rising edge of Initb Hold time on M20 mode pins after the rising edge of Initb Parallel NOR Flash Prom output-enable time Symbol Description Requirement UnitsParallel NOR Flash Prom read access time Parallel NOR Flash Prom chip-select time INTEST, EXTEST, Sample Ieee 1149.1/1553 Jtag Test Access Port Timing DSP48A timing in and Table Diffhstli and Diffhstliii to , , and . Updated Tmds DC DC and Switching Characteristics Type/Color Description Pin Names in Type Code Types of Pins on Spartan-3A DSP FPGAsPin Types Pinout Descriptions Types of Pins on Spartan-3A DSP FPGAs Package Pins by TypePower and Ground Supply Pins by Package Maximum User I/O by Package Pinout Descriptions Package Thermal CharacteristicsSpartan-3A DSP Package Thermal Characteristics Pinout Table CS484 484-Ball Chip-Scale Ball Grid ArraySpartan-3A DSP CS484 Pinout Bank Pin Name CS484 Type Ball Pinout Descriptions Spartan-3A DSP CS484 Pinout AA3 Dual VCCO1AA4 AA6 Input VCCO2 VCCO2 AA5 Vcco AA9VCCO2 Vcco AA1 Vref GND AB1 VCCO3 VccoGND AA7 Vccaux TCK Vccaux Progb Config DoneJtag Vccaux TMS Jtag TDO Footprint Migration Differences User I/Os by BankUser I/Os Per Bank for the XC3SD1800A in the CS484 Package User I/Os Per Bank for the XC3SD3400A in the CS484 Package Left Half of Package top view CS484 Footprint Right Half of CS484 Package top view Pinout Table FG676 676-Ball Fine-Pitch Ball Grid ArraySpartan-3A DSP FG676 Pinout for Spartan-3A DSP FG676 Pinout for XC3SD1800A Fpga IOL26N0/GCLK7 IOL26P0/GCLK6 IOL30P1/RHCLK0 IOL30N1/RHCLK1IOL33P1/RHCLK4 IOL31P1/RHCLK2 IOL27P2/GCLK0 IOL17P2/RDWRB AF4 AF3AF5 AF7 Input AB9 IP2/VREF2 AB6 VrefIOL30N2/MOSI/CSIB IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 Vref IOL34N3/LHCLK5 IOL33P3/LHCLK2IOL34P3/LHCLK4 IOL35N3/LHCLK7 AE2 Vref AE1 InputAD1 AD2 GND AF1 AF6 Vccaux Progb Config TDI Jtag TDOGND AD3 AD8 GND AA1 AA6 User I/Os Per Bank for the XC3SD1800A in the FG676 Package User I/Os by BankTop 128 Right 519 314 FG676 Package Footprint for XC3SD1800A Fpga top view FG676 Footprint TDO Bank XC3SD3400A Pin Name FG676 Type Ball Spartan-3A DSP FG676 Pinout for XC3SD3400A FpgaIOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0 IOL01P0 G20 IP1/VREF1 VCCO0 Vcco IOL01P1/HDC IOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16 IOL34P1/IRDY1/RHCLK6 IOL12P2 Y10 IOL05N1 AC25 IOL06P1T25 IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22 VCCO2 AF7 Vcco AE5 IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IOL53P3 IOL53N3 IP3IOL36N3 IOL37P3 AA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND IP3/VREF3 VrefIOL10N3 IOL03N3 IP3 GND AC5 AC7 GND AD3 AD5 AD8GND AB3 GND AA1 AA4 AA6 Vccint AA8 Vccaux AF2 AB4 AB5 User I/Os Per Bank for the XC3SD3400A in the FG676 Package Vref are on Input pinsTop 111 Right Bottom 112 Left Pinout Descriptions FG676 Package Footprint for XC3SD3400A Fpga top view VCCO0 VREF1 VREF1 FG676 Footprint Migration Differences Pinout Descriptions FG676 Footprint Migration Differences Migration Recommendations Fpga and XC3SD3400A Fpga . Minor edits SPARTAN-3A DSP Pinout Descriptions