Xilinx DS610 manual FG676 Footprint, FG676 Package Footprint for XC3SD1800A Fpga top view

R

FG676 Footprint -

XC3SD1800A FPGA

Left Half of Package (top view)

I/O: Unrestricted,

314general-purpose user I/O.

INPUT: Unrestricted,

82general-purpose input pin.

DUAL: Configuration,

52AWAKE pins, then possible user I/O.

VREF: User I/O or input

39voltage reference for bank.

CLK: User I/O, input, or

32clock buffer input.

CONFIG: Dedicated

3configuration pins, SUSPEND pin.

JTAG: Dedicated JTAG

4port pins.

GND: Ground

77

VCCO: Output voltage

36supply for bank.

VCCINT: Internal core

23supply voltage (+1.2V).

VCCAUX: Auxiliary supply

14voltage.

Note: The boxes with triangles inside indicate pin differences from the XC3SD3400A device.

Please see the "Footprint Migration Differences" section for more information.

Pinout Descriptions

Bank 0

1

2

3

4

5

6

7

8

9

10

11

12

13

A

GND

PROG_

I/O

I/O

INPUT

GND

INPUT

I/O

I/O

I/O

GND

I/O

INPUT

∇

∇

B

L51P_0

L45P_0

L38P_0

L36P_0

L33P_0

L29P_0

B

I/O

I/O

I/O

I/O

VCCO_0

I/O

I/O

I/O

I/O

I/O

VCCO_0

I/O

I/O

L28P_0

L02N_3

L02P_3

L51N_0

L45N_0

L41P_0

L42P_0

L38N_0

L36N_0

L33N_0

L29N_0

GCLK10

INPUT

INPUT

INPUT

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

C

L04N_3

L04P_3

GND

GND

VREF_3

∇

L28N_0

∇

L44P_0

L41N_0

L42N_0

L40P_0

L34P_0

L32P_0

L30N_0

∇

GCLK11

INPUT

INPUT

I/O

INPUT

I/O

INPUT

I/O

I/O

I/O

I/O

I/O

D

L08N_3

L08P_3

TMS

INPUT

∇

L32N_0

∇

∇

L06P_3

L44N_0

VREF_0

L40N_0

L37N_0

L34N_0

VREF_0

L30P_0

E

I/O

VCCO_3

I/O

I/O

VCCAUX

INPUT

I/O

VCCO_0

INPUT

I/O

INPUT

I/O

VCCO_0

∇

∇

L11P_3

L07P_3

L06N_3

L48N_0

L37P_0

L31P_0

F

GND

I/O

I/O

I/O

I/O

GND

I/O

I/O

INPUT

INPUT

GND

I/O

I/O

L52P_0

∇

∇

L27P_0

L11N_3

L14N_3

L07N_3

L09P_3

L48P_0

L31N_0

VREF_0

GCLK8

INPUT

INPUT

I/O

I/O

INPUT

I/O

I/O

I/O

I/O

INPUT

I/O

I/O

G

L16N_3

L16P_3

L12P_3

TDI

L52N_0

L27N_0

∇

∇

L14P_3

L09N_3

∇

L03P_3

PUDC_B

L47P_0

L46P_0

VREF_0

L35P_0

GCLK9

I/O

I/O

INPUT

I/O

I/O

I/O

I/O

I/O

H

GND

L12N_3

VCCO_3

GND

VCCO_0

INPUT

L17N_3

L17P_3

VREF_3

L10N_3

L03N_3

L47N_0

L46N_0

L35N_0

∇

J

INPUT

INPUT

INPUT

I/O

I/O

I/O

I/O

I/O

I/O

INPUT

I/O

I/O

INPUT

L20N_3

L24P_3

VREF_3

L20P_3

L19N_3

L19P_3

L13N_3

L10P_3

L01P_3

L01N_3

L43P_0

L39P_0

K

INPUT

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GND

I/O

I/O

VCCAUX

L24N_3

L23N_3

L23P_3

L22N_3

L22P_3

L18P_3

L13P_3

L05N_3

L05P_3

L43N_0

L39N_0

L

GND

VCCO_3

I/O

I/O

VCCAUX

GND

I/O

VCCO_3

I/O

I/O

GND

VCCINT

GND

L25N_3

L25P_3

L18N_3

L15N_3

L15P_3

M

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

VCCINT

GND

VCCINT

L29N_3

L29P_3

L27N_3

L27P_3

L28P_3

L28N_3

L26N_3

L26P_3

L21N_3

L21P_3

VREF_3

3

I/O

I/O

I/O

I/O

I/O

I/O

I/O

N

GND

GND

L35P_3

VCCAUX

GND

VCCINT

VCCINT

L32P_3

L32N_3

L31P_3

L31N_3

L30N_3

L30P_3

TRDY2

Bank

I/O

L33N_3

I/O

I/O

I/O

I/O

I/O

I/O

I/O

LHCLK0

LHCLK1

LHCLK6

P

L33P_3

I/O

L34N_3

L34P_3

VCCO_3

L39N_3

L39P_3

L41P_3

L41N_3

L35N_3

VCCINT

GND

VCCINT

IRDY2

LHCLK2

LHCLK5

LHCLK4

LHCLK7

LHCLK3

R

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GND

VCCINT

GND

L36P_3

L43P_3

L36N_3

L37P_3

L37N_3

L40P_3

L40N_3

L45N_3

L45P_3

L43N_3

VREF_3

VREF_3

T

GND

VCCO_3

I/O

I/O

I/O

GND

I/O

VCCO_3

I/O

I/O

VCCINT

GND

VCCINT

L38P_3

L38N_3

L42P_3

L51P_3

L48N_3

L48P_3

U

I/O

I/O

INPUT

I/O

I/O

I/O

I/O

I/O

I/O

GND

I/O

VCCINT

GND

L44P_3

L44N_3

L46P_3

L42N_3

L49P_3

L51N_3

L56P_3

L56N_3

L61P_3

L13N_2

V

I/O

I/O

GND

INPUT

I/O

I/O

I/O

I/O

VCCAUX

I/O

I/O

I/O

I/O

L47P_3

L47N_3

L46N_3

L49N_3

L59N_3

L59P_3

L61N_3

L09P_2

L13P_2

L16P_2

L20P_2

W

INPUT

INPUT

I/O

I/O

VCCO_3

I/O

I/O

GND

I/O

I/O

VCCO_2

I/O

I/O

L50N_3

L50P_3

L52P_3

L52N_3

L63N_3

L63P_3

L05P_2

L09N_2

L16N_2

L20N_2

VREF_3

I/O

I/O

INPUT

INPUT

I/O

I/O

I/O

INPUT

I/O

I/O

INPUT

I/O

I/O

Y

L54P_3

L54N_3

L02P_2

∇

∇

L17P_2

L25N_2

L53P_3

L53N_3

∇

∇

L57P_3

L57N_3

L05N_2

L12P_2

M2

RDWR_B

GCLK13

A

I/O

I/O

INPUT

INPUT

I/O

INPUT

INPUT

I/O

I/O

I/O

GND

L58P_3

L58N_3

GND

GND

A

L55P_3

L55N_3

∇

VREF_3

L02N_2

∇

VREF_2

L12N_2

L17N_2

L25P_2

CSO_B

VS2

GCLK12

∇

A

I/O

INPUT

INPUT

INPUT

I/O

I/O

INPUT

I/O

VCCO_3

L62P_3

L62N_3

VCCAUX

VCCO_2

VREF_2

VCCAUX

INPUT

B

L60P_3

∇

∇

VREF_2

L14N_2

L15P_2

∇

L21P_2

A

I/O

I/O

I/O

I/O

INPUT

I/O

INPUT

I/O

I/O

INPUT

I/O

I/O

INPUT

C

L60N_3

L64P_3

L64N_3

L01P_2

∇

L08P_2

∇

L14P_2

L15N_2

VREF_2

L23N_2

L21N_2

M1

A

I/O

I/O

GND

I/O

INPUT

I/O

I/O

GND

INPUT

INPUT

I/O

INPUT

GND

D

L65P_3

L65N_3

L01N_2

∇

L08N_2

L11P_2

L23P_2

VREF_2

M0

A

INPUT

INPUT

I/O

I/O

VCCO_2

I/O

I/O

I/O

I/O

I/O

VCCO_2

I/O

I/O

E

L66P_3

L66N_3

L06P_2

L07P_2

L10N_2

L11N_2

L18P_2

L19P_2

L22P_2

L24N_2

L26N_2

VREF_3

VS1

D7

D4

GCLK15

A

GND

INPUT

I/O

I/O

I/O

GND

INPUT

I/O

I/O

I/O

GND

I/O

I/O

F

∇

L06N_2

L07N_2

L10P_2

∇

L18N_2

L19N_2

L22N_2

L24P_2

L26P_2

VS0

D6

D5

GCLK14

Bank 2

Figure 17: FG676 Package Footprint for XC3SD1800A FPGA (top view)

DS610-4 (v2.0) July 16, 2007 www.xilinx.com 81

Product Specification