User I/Os by Bank, Top 128 Right, 519 314

Pinout Descriptions

User I/Os by Bank

Table 64 indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The AWAKE pin is counted as a Dual-Purpose I/O.

Table 64: User I/Os Per Bank for the XC3SD1800A in the FG676 Package

Package		Maximum I/Os		All Possible I/O Pins by Type
		and
	I/O Bank	and	I/O	INPUT	DUAL	VREF(1)	CLK
Edge	I/O Bank	Input-Only	I/O	INPUT	DUAL	VREF(1)	CLK
Top	0	128	82	28	1	9	8

Right	1	130	67	15	30	10	8

Bottom	2	129	68	21	21	11	8

Left	3	132	97	18	0	9	8

TOTAL		519	314	82	52	39	32

Notes:

1.28 VREF are on INPUT pins.

80	www.xilinx.com	DS610-4 (v2.0) July 16, 2007
		Product Specification

Page 80

Image 80

Xilinx DS610 manual User I/Os by Bank, User I/Os Per Bank for the XC3SD1800A in the FG676 Package, Top 128 Right, 519 314

Contents

Product Specification DS610-1 v2.0 July 16DS610-2 v2.0 July 16 DS610-3 v2.0 July 16 Data Sheet Spartan-3A and Spartan-3A DSP Fpga Differences FeaturesIntroduction Configuration Architectural OverviewCapabilities Introduction and Ordering Information DCM CS484 FG676 Device CSG484 FGG676 User Diff XC3SD1800A519 227 XC3SD3400A Package Marking Ordering InformationStandard Packaging Pb-Free Packaging Revision History Date Version Revision Introduction and Ordering Information Added Low-power options no changes to this module DS610-2 v2.0 July 16 Functional Description DC Electrical Characteristics Symbol Description Conditions Min Max UnitsAbsolute Maximum Ratings Absolute Maximum Ratings Power Supply Specifications DC and Switching CharacteristicsSupply Voltage Thresholds for Power-On Reset Symbol Description Min Max Units = GND General DC Characteristics for I/O PinsSymbol Description Test Conditions Min Typ Max Units Quiescent Supply Current Characteristics Typical2 Commercial Industrial Symbol Description DeviceQuiescent Current Requirements Maximum2 Attribute Min Nom Max Single-Ended I/O StandardsCCO for Drivers Test Logic Level Conditions Characteristics AttributeTest Logic Level Conditions Attribute Max Min Min Nom Max Min mV Nom mV Max mV Differential I/O StandardsIostandard Attribute CCO for Drivers Iostandard Attribute Min mV Typ mV Max mV Device DNA Identifier Memory Characteristics Symbol Description Minimum UnitsDevice DNA Data Retention, Read Endurance External Termination Requirements for Differential I/O Switching Characteristics Software Version Requirements Spartan-3A DSP v1.29 Speed Grade Designations Sign Up for Alerts on Xilinx MySupportSpartan-3A DSP Speed File Version History Timing Pin-to-Pin Clock-to-Output Times for the IOB Output PathRate, without DCM At the Output pin. The DCM is not Use Ifddelayvalue = Hold Times Symbol Description Conditions Device Min Units Setup TimesSet/Reset Pulse Width Speed Grade Ioplid Single-Ended Standards Lvttl LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12PCI333 PCI663 Differential Standards Timing for the IOB Three-State Path Set/Reset TimesAsynchronous Output Enable/Disable Times QuietIO 27.67 QuietIO QuietIO 25.92 QuietIO 24.97 LVDS25 LVDS33 BLVDS25 MINILVDS25 MINILVDS33 LVPECL25 Inputs Only Signal Standard Inputs Outputs Timing Measurement MethodologyTest Methods for Timing Measurement at I/Os Inputs Vicm + RT ΩDifferential Device CS484 FG676 XC3SD1800A XC3SD3400A Simultaneously Switching Output GuidelinesEquivalent VCCO/GND Pairs per Bank CS484, FG676 Signal Standard Top, Bottom Left, RightPackage Type QuietIO PCI333 PCI663 Differential Standards Number of I/O Pairs or Channels Clock Timing Configurable Logic Block CLB TimingCLB Slicem Timing Clock Distribution Switching Characteristics Clock Buffer/Multiplexer Switching CharacteristicsCLB Shift Register Switching Characteristics Clock Frequency Block RAM TimingBlock RAM Timing Setup Times for the DSP48A Speed Grade Symbol DescriptionSetup Times of Data Pins to the Pipeline Register Clock DSP48A Timing Clock to Out from Pipeline Register Clock to Output Pins Clock to Out from Input Register Clock to Output PinsCombinatorial Delays from Input Pins to Output Pins Maximum Frequency Delay-Locked Loop DLL Input Clock Jitter Tolerance Delay Path Variation4Digital Clock Manager DCM Timing Recommended Operating Conditions for the DLL Speed Grade Symbol Description Switching Characteristics for the DFS Speed Grade Symbol Description Units Min MaxDigital Frequency Synthesizer DFS Recommended Operating Conditions for the DFS Phase Shifter PS Switching Characteristics for the PS in Variable Phase ModePhase Shifting Range Miscellaneous DCM Timing DNA Port Timing Dnaport Interface Timing Suspend Mode Timing Entering Suspend Mode Exiting Suspend ModeEntering Suspend Mode Symbol Description Min Typ Max Units All Speed Grades Symbol Description Device Min Max Units Configuration and Jtag TimingGeneral Configuration Power-On/Reconfigure Timing Configuration Clock Cclk Characteristics Master Mode Cclk Output Period by ConfigRate Option SettingCclk clock period by 11.2 Master Mode Cclk Output Minimum Low and High Time Slave Mode Cclk Input Low and High TimeEquivalent Cclk clock frequency Cclk Low and High time Min Max Units Clock-to-Output Times Master Serial and Slave Serial Mode TimingSlave All Speed Grades Symbol Description Slave Parallel Mode Timing Serial Peripheral Interface SPI Configuration Timing Symbol Description Minimum Symbol Description Requirement Units Byte Peripheral Interface BPI Configuration Timing Symbol Description Minimum Maximum UnitsSetup time on M20 mode pins before the rising edge of Initb Hold time on M20 mode pins after the rising edge of Initb Symbol Description Requirement Units Parallel NOR Flash Prom output-enable timeParallel NOR Flash Prom read access time Parallel NOR Flash Prom chip-select time Ieee 1149.1/1553 Jtag Test Access Port Timing INTEST, EXTEST, Sample Diffhstli and Diffhstliii to , , and . Updated Tmds DC DSP48A timing in and Table DC and Switching Characteristics Type/Color Description Pin Names in Type Code Types of Pins on Spartan-3A DSP FPGAsPin Types Package Pins by Type Pinout Descriptions Types of Pins on Spartan-3A DSP FPGAsPower and Ground Supply Pins by Package Maximum User I/O by Package Pinout Descriptions Package Thermal CharacteristicsSpartan-3A DSP Package Thermal Characteristics CS484 484-Ball Chip-Scale Ball Grid Array Pinout TableSpartan-3A DSP CS484 Pinout Bank Pin Name CS484 Type Ball Pinout Descriptions Spartan-3A DSP CS484 Pinout VCCO1 AA3 DualAA4 AA6 Input VCCO2 AA5 Vcco AA9 VCCO2VCCO2 Vcco AA1 Vref GND AB1 VCCO3 VccoGND AA7 Vccaux Progb Config Done Vccaux TCKJtag Vccaux TMS Jtag TDO User I/Os by Bank Footprint Migration DifferencesUser I/Os Per Bank for the XC3SD1800A in the CS484 Package User I/Os Per Bank for the XC3SD3400A in the CS484 Package CS484 Footprint Left Half of Package top view Right Half of CS484 Package top view FG676 676-Ball Fine-Pitch Ball Grid Array Pinout TableSpartan-3A DSP FG676 Pinout for Spartan-3A DSP FG676 Pinout for XC3SD1800A Fpga IOL26P0/GCLK6 IOL26N0/GCLK7 IOL30N1/RHCLK1 IOL30P1/RHCLK0IOL33P1/RHCLK4 IOL31P1/RHCLK2 IOL17P2/RDWRB IOL27P2/GCLK0 AF3 AF4AF5 AF7 Input IP2/VREF2 AB6 Vref AB9IOL30N2/MOSI/CSIB IOL02N2/CSOB AA7 Dual IP2/VREF2 AA9 Vref IOL33P3/LHCLK2 IOL34N3/LHCLK5IOL34P3/LHCLK4 IOL35N3/LHCLK7 AE1 Input AE2 VrefAD1 AD2 Vccaux Progb Config TDI Jtag TDO GND AF1 AF6GND AD3 AD8 GND AA1 AA6 User I/Os by Bank User I/Os Per Bank for the XC3SD1800A in the FG676 PackageTop 128 Right 519 314 FG676 Footprint FG676 Package Footprint for XC3SD1800A Fpga top view TDO Spartan-3A DSP FG676 Pinout for XC3SD3400A Fpga Bank XC3SD3400A Pin Name FG676 Type BallIOL16P0 G15 IOL08N0 G17 IOL02P0/VREF0 IOL01P0 G20 VCCO0 Vcco IOL01P1/HDC IP1/VREF1 IOL34P1/IRDY1/RHCLK6 IOL58N1 G22 IOL51P1 G23 IOL51N1 G24 DS610-4 v2.0 July 16 IOL12P2 Y10 IOL05N1 AC25 IOL06P1T25 IOL23N2 AC11 IOL21N2 AC12 IP2 AC13 IOL29N2 AC14 IOL30P2 AC15 IOL38P2 AC16 IP2 AC17IOL40N2 AC19 IOL41N2 AC20 IOL45N2 AC21 IO2 AC22 VCCO2 AF7 Vcco AE5 IOL32P3/LHCLK0 Lhclk IOL32N3/LHCLK1 IOL35P3/TRDY2/LHCLK6 IOL53P3 IOL53N3 IP3IOL36N3 IOL37P3 AA3 IP3/VREF3 AA5 Vref VCCO3 Vcco AB2 GND IP3/VREF3 VrefIOL10N3 IOL03N3 IP3 GND AD3 AD5 AD8 GND AC5 AC7GND AB3 GND AA1 AA4 AA6 Vccaux AF2 AB4 AB5 Vccint AA8 Vref are on Input pins User I/Os Per Bank for the XC3SD3400A in the FG676 PackageTop 111 Right Bottom 112 Left FG676 Package Footprint for XC3SD3400A Fpga top view Pinout Descriptions VCCO0 VREF1 FG676 Footprint Migration Differences VREF1 Migration Recommendations Pinout Descriptions FG676 Footprint Migration Differences SPARTAN-3A DSP Fpga and XC3SD3400A Fpga . Minor edits Pinout Descriptions

Pinout Descriptions

User I/Os by Bank

Table 64: User I/Os Per Bank for the XC3SD1800A in the FG676 Package

CLK

Input-Only

Top

128

Right

519

314