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| Switch Settings (Continued) |
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SWITCH NAME | SWITCH | SETTING | FUNCTION |
| CHECK |
NUMBER | POSITION |
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SW0 |
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| • Uses the internal clock as the | receive |
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| ON | clock when the No. 0 Port is synchro- |
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| nous. |
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| 5 |
| • When the No. 0 Port is asynchronous. |
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| Note 4 |
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| Enables receive clock from the DCE (Mo- |
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| OFF | dem) side when the No. 0 Port is synchro- |
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| nous. (Clock is received at the RXC |
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| terminal) |
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| Set No. 0 port forcibly in a state which DSR |
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| ON | signal is always provided. Force DSR sig- |
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| 6 |
| nal high for port 0. No SMDR buffering. |
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| Note 5 |
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| Receive DSR signal from the DCE on No. |
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| OFF | 0 port. Detect DSR signal from DCE for |
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| port 0. Allows SMDR records to buffer. |
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| Set No. 1 port forcibly in a state which DSR |
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| ON | signal is always provided. Force DSR sig- |
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| 7 |
| nal high for port 1. No SMDR buffering. |
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| Note 5 |
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| Receive DSR signal from the DCE on No. |
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| OFF | 1 port. Detect DSR signal from DCE for |
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| port 1. Allows SMDR records to buffer. |
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| Set No. 2 port forcibly in a state which |
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| ON | DSR signal is always provided. Force DSR |
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| 8 |
| signal high for port 2. No SMDR buffering. |
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| Note 5 |
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| Receive DSR signal from the DCE on No. |
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| OFF | 2 port. Detect DSR signal from DCE for |
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| port 2. Allows SMDR records to buffer. |
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The figure in the SWITCH NAME column and the position in 
in the SETTING POSITION col- umn indicate the standard setting of the switch. When the switch is not set as shown by the figure and 
, the setting of the switch varies with the system concerned.
Page 57
Revision 2.0
