Samsung S3C84E5 user manual Level

INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9

Table 5-1. Interrupt Vectors

Vector Address		Interrupt Source	Request		Reset/Clear
Decimal	Hex		Interrupt	Priority in	H/W	S/W
Value	Value		Level	Level
256	100H	Basic timer (WDT) overflow	nRESET	–	Ö
230	E6H	UART transmit	IRQ7	1		Ö
228	E4H	UART receive		0		Ö
226	E2H	P4.2 external interrupt	IRQ6	2		Ö
224	E0H	P4.1 external interrupt		1		Ö
222	DEH	P4.0 external interrupt		0		Ö
220	DCH	P2.7 external interrupt	IRQ5	3		Ö
218	DAH	P2.6external interrupt		2		Ö
216	D8H	P2.5 external interrupt		1		Ö
214	D6H	P2.4 external interrupt		0		Ö
212	D4H	P2.3 external interrupt	IRQ4	3		Ö
210	D2H	P2.2 external interrupt		2		Ö
208	D0H	P2.1external interrupt		1		Ö
206	CEH	P2.0 external interrupt		0		Ö
204	CCH	Watch timer	IRQ3	–		Ö
202	CAH	Timer 1(1) overflow	IRQ2	3	Ö	Ö
200	C8H	Timer 1(1) match/capture		2	Ö	Ö
198	C6H	Timer 1(0) overflow		1	Ö	Ö
196	C4H	Timer 1(0) match/capture		0	Ö	Ö
194	C2H	Timer A overflow	IRQ1	1	Ö	Ö
192	C0H	Timer A match/capture		0	Ö	Ö
190	BEH	Timer B underflow	IRQ0	–	Ö

NOTES:

1.Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.

2.If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority over one with a higher vector address. The priorities within a given level are fixed in hardware.

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