Samsung S3C84E5 Figure 9-7. Port 2 Interrupt Pending Register (P2INTPND)

I/O PORTS S3C84E5/C84E9/P84E9
9-10
Port 2 Interrupt Pending Register (P2INTPND)
EDH, Set1, Bank0, R/W, Reset value="00"
.7 .6 .5 .4 .3 .2 .1 .0
MSB LSB
[.7] P2.7/PND7, Interrupt Pending Bit
0 = No interrupt pending (when read) / Pending bit clear (when write)
1 = Interrupt is pending (when read) / No effect (when write)
[.6] P2.6/PND6, Interrupt Pending Bit
0 = No interrupt pending (when read) / Pending bit clear (when write)
1 = Interrupt is pending (when read) / No effect (when write)
[.5] P2.5/PND5, Interrupt Pending Bit
0 = No interrupt pending (when read) / Pending bit clear (when write)
1 = Interrupt is pending (when read) / No effect (when write)
[.4] P2.4/PND4, Interrupt Pending Bit
0 = No interrupt pending (when read) / Pending bit clear (when write)
1 = Interrupt is pending (when read) / No effect (when write)
[.3] P2.3/PND3, Interrupt Pending Bit
0 = No interrupt pending (when read) / Pending bit clear (when write)
1 = Interrupt is pending (when read) / No effect (when write)
[.2] P2.2/PND2, Interrupt Pending Bit
0 = No interrupt pending (when read) / Pending bit clear (when write)
1 = Interrupt is pending (when read) / No effect (when write)
[.1] P2.1/PND1, Interrupt Pending Bit
0 = No interrupt pending (when read) / Pending bit clear (when write)
1 = Interrupt is pending (when read) / No effect (when write)
[.0] P2.0/PND0, Interrupt Pending Bit
0 = No interrupt pending (when read) / Pending bit clear (when write)
1 = Interrupt is pending (when read) / No effect (when write)
Figure 9-7. Port 2 Interrupt Pending Register (P2INTPND)