S3C84E5/C84E9/P84E9 ADDRESS SPACES
2-3
REGISTER ARCHITECTURE In the S3C84E5/C84E9/P84E9 implementation, the upper 64-byte area of register files is expanded two 64-byte
areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0
and bank 1), and the lower 32-byte area is a single 32-byte common area. set 2 is logically expanded 2 separately
addressable register pages, page 0–page 1.
In case of S3C84E5/C84E9/P84E9 the total number of addressable 8-bit registers is 590. Of these 590 registers, 16
bytes are for CPU and system control registers, 46 bytes are for peripheral control and data registers, 16 bytes are
used as a shared working registers, and 512 registers are for general-purpose use.
You can always address set 1 register location, regardless of which of the 2 register pages is currently selected. The
set 1 locations, however, can only be addressed using direct addressing modes.
The extension of register space into separately addressable areas (sets, banks, and pages) is supported by various
addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer (PP).
Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2–1.
Table 2-1. S3C84E5/C84E9/P84E9 Register Type Summary
Register Type Number of Bytes
General-purpose registers (including 16-byte common
working register area, expanded 2 separately addressable
register pages (1Page occupies 192-byte prime register
area and the 64-byte set 2 area)
CPU and system control registers
Mapped clock, peripheral, I/O control, and data registers
528
16
46
Total Addressable Bytes 590