Samsung S3C84E5 Uart Interrupt Pending Register Uartpnd, Must keep always, Always, 13-4

UART S3C84E5/C84E9/P84E9

UART INTERRUPT PENDING REGISTER (UARTPND)

The UART interrupt pending register, UARTPND is located at address F4H. It contains the UART data transmit interrupt pending bit (UARTPND.0) and the receive interrupt pending bit (UARTPND.1).

In mode 0 of the UART module, the receive interrupt pending flag UARTPND.1 is set to "1" when the 8th receive data bit has been shifted. In mode 1 or 2, the UARTPND.1 bit is set to "1" at the halfway point of the stop bit's shift time. When the CPU has acknowledged the receive interrupt pending condition, the UARTPND.1 flag must be cleared by software in the interrupt service routine.

In mode 0 of the UART module, the transmit interrupt pending flag UARTPND.0 is set to "1" when the 8th transmit data bit has been shifted. In mode 1 or 2, the UARTPND.0 bit is set at the start of the stop bit. When the CPU has acknowledged the transmit interrupt pending condition, the UARTPND.0 flag must be cleared by software in the interrupt service routine.

UART Pending Register (UARTPND)

F4H, Set1, Bank 0, R/W, Reset Value: 00H

MSB .7 .6 PEN RPE .3 .2 RIP TIP LSB

Not used		Not used		UART transmit interrupt pending flag
(must keep always 0)		(must keep
				0 = Not pending
		always 0)
UART parity enable/disable:				0 = Clear pending bit (when write)
				1 = Interrupt pending
0 = Disable
1 = Enable	UART receive parity error:		UART receive interrupt pending flag:
	0 = No error		0 = Not pending
	1 = Parity error		0 = Clear pending bit (when write)
			1 = Interrupt pending

NOTES:

1. In order to clear a data transmit or receive interrupt pendingflag, you must write a "0" to the appropriate pending bit. A "0" has no effect.

2. To avoid errors, we recommend using load instruction (except for LDB), when manipulating UARTPND values.

3. Parity enable and parity error check can be available in 9-bit UART mode (Mode 2) only.

4. Parity error bit (RPE) will be refreshed whenever 8th receive data bit has been shifted.

Figure 13-2. UART Interrupt Pending Register (UARTPND)

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