Samsung S3C84E5 Figure 9-2. Port 0 Low Byte Control Register (P0CONL)

I/O PORTS S3C84E5/C84E9/P84E9
9-4
Port 0 Control Register, Low Byte (P0CONL)
E7H, Set1, Bank0, R/W, Reset value="0FH"
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
[.7-.6] P0.3/T1CK1 Configuration Bits
0 0 = Input mode with pull-up; T1CK1 input
0 1 = Input mode; T1CK1 input
1 X = Push-pull output mode
[.5-.4] P0.2/T1CAP1 Configuration Bits
0 0 = Input mode with pull-up; T1CAP1 input
0 1 = Input mode; T1CAP1 input
1 X = Push-pull output mode
[.3-.2] P0.1/XTout Configuration Bits
0 0 = Input mode with pull-up
0 1 = Input mode
1 0 = Push-pull output mode
1 1 = Alternative function mode: Sub oscillator output (XTout)
[.1-.0] P0.0/XTin Configuration Bits
0 0 = Input mode with pull-up
0 1 = Input mode
1 0 = Push-pull output mode
1 1 = Alternative function mode: Sub oscillator input (XTin)
Figure 9-2. Port 0 Low Byte Control Register (P0CONL)